Abstract: A method for demosaicing a raw image includes: (1) horizontally-interpolating a green channel formed of primary pixel-values Bg(x,y)g to yield a horizontally-interpolated green channel that includes both Bg(x,y)g and non-primary pixel-values Igh(x,y)r,b; (2) modifying each Igh(x,y)r,b, by horizontally-neighboring pixel-values, to yield a refined horizontally-interpolated green channel; (3) vertically-interpolating the green channel to yield a vertically-interpolated green channel that includes pixel-values Igv(x,y)r,b; (4) modifying each Igv(x,y)r,b by vertically-neighboring pixel-values, to yield a refined vertically-interpolated green channel; (5) generating a full-resolution green channel from the refined interpolated green channels and gradients thereof; (6) generating a full-resolution red channel by determining red pixel-values from a local-red mean value of neighboring pixel-values and the full-resolution green channel; (7) generating a full-resolution blue channel by determining pixel-values from a lo

Abstract: A four-surface, near-infrared wafer-level lens system for imaging a scene onto an image plane includes (a) a first wafer-level lens having a first convex lens surface facing the scene and a second concave lens surface facing the image plane, and (b) a second wafer-level lens disposed between the first wafer-level lens and the image plane and including a third concave lens surface facing the scene and a fourth aspheric convex lens surface facing the image plane. The four-surface, near-infrared wafer-level lens system is further characterized by an image resolution corresponding to at least 60% contrast of 2 line pairs per millimeter in object plane across a scene portion having at least 10 millimeters extent in the object plane.

Abstract: An image sensor pixel array comprises a center region and two parallel edge regions, wherein the center region is between the two parallel edge regions. The center region comprises a plurality of image pixels disposed along first sub-array of rows and columns, wherein each of the plurality of image pixels comprises a first micro-lens (ML) formed at an offset position above a first light receiving element as a countermeasure for shortening of exit pupil distance of the image pixel in the center region, and each of the two parallel edge regions comprises a plurality of phase detection auto-focus (PDAF) pixels disposed along second sub-array of rows and columns, wherein each of the plurality of PDAF pixels comprises a second micro-lens (ML) formed at an alignment position above a second light receiving element; and at least one of the PDAF pixels is located at a distance away from center of the edge region to receive incident light along an injection tilt angle.

Abstract: An image sensor includes a substrate, a plurality of light sensitive pixels, a first plurality of color filters, a plurality of reflective sidewalls, and a second plurality of color filters. The light sensitive pixels are formed on said substrate. The first plurality of color filters is disposed over a first group of the light sensitive pixels. The reflective sidewalls are formed on each side of each of the first plurality of color filters. The second plurality of color filters are disposed over a second group of light sensitive pixels and each color filter of the second plurality of color filters is separated from each adjacent filter of said first plurality of color filters by one of the reflective sidewalls. In a particular embodiment an etch-resistant layer is disposed over the first plurality of color filters and the second group of light sensitive pixels.

Abstract: A pixel cell includes a photodiode disposed in a semiconductor material to accumulate image charge in response to incident light and a global shutter gate transistor coupled to the photodiode to selectively deplete the image charge from the photodiode. A storage transistor is disposed in the semiconductor material to store the image charge. An isolation structure is disposed in the semiconductor material proximate to the storage transistor to isolate a sidewall of the storage transistor from stray light and stray charge. The isolation structure is filled with tungsten and is coupled to receive a variable bias signal to control a bias of the isolation structure. The variable bias signal is set to a first bias value during a transfer of the image charge to the storage transistor. The variable bias signal is set to a second bias value during a transfer of the image charge from the storage transistor.

Abstract: An image sensor includes a plurality of photodiodes disposed in a semiconductor material to convert image light into image charge. A floating diffusion is disposed proximate to the plurality of photodiodes to receive the image charge from the plurality of photodiodes. A plurality of transfer transistors is coupled to transfer the image charge from the plurality of photodiodes into the floating diffusion in response to a voltage applied to the gate terminal of the plurality of transfer transistors. A first trench isolation structure extends from a frontside of the semiconductor material into the semiconductor material and surrounds the plurality of photodiodes. A second trench isolation structure extends from a backside of the semiconductor material into the semiconductor material. The second trench isolation structure is disposed between individual photodiodes in the plurality of photodiodes.

Abstract: A resonant-filter image sensor includes a pixel array including a plurality of pixels and a microresonator layer above the pixel array. The microresonator layer includes a plurality of microresonators formed of a first material with an extinction coefficient less than 0.02 at a free-space wavelength of five hundred nanometers. Each of the plurality of pixels may have at least one of the plurality of microresonators at least partially thereabove. The resonant-filter image sensor may further include a layer covering the microresonator layer that has a second refractive index less than a first refractive index, the first refractive index being the refractive index of the first material. Each microresonator may be one of a parallelepiped, a cylinder, a spheroid, and a sphere.

Abstract: A method of fanning an electrical connection in a liquid crystal on silicon (LCOS) device, comprising: providing a silicon substrate including a first surface and a second surface, wherein the silicon substrate includes an conductive pad at the first surface; providing a cover glass panel that includes a cover glass, a transparent electrode layer formed upon the cover glass, and a first sealing material layer formed upon the transparent electrode layer; forming a second sealing material layer upon the first surface of the silicon substrate, wherein the second sealing material layer covers the conductive pad; forming a display layer, comprising a liquid crystal portion, a first seal portion, and a second seal portion, upon the second sealing material layer; wherein the first seal portion and the second seal portion are situated to form a space between them; and wherein the space is situated on top of the conductive pad; placing the cover glass panel upon the display layer, wherein the first sealing material la

Abstract: A method for manufacturing a high-dynamic-range color image sensor includes (a) depositing a color filter layer on a silicon substrate having a photosensitive pixel array with a plurality of first pixels and a plurality of second pixels, to form (i) a plurality of first color filters above a first subset of each of the plurality of first pixels and the plurality of second pixels and (ii) a plurality of second color filters above a second subset of each of the plurality of first pixels and the plurality of second pixels, wherein thickness of the second color filters exceeds thickness of the first color filters, and (b) depositing, on the color filter layer, a dynamic-range extending layer including grey filters above the second pixels to attenuate light propagating toward the second pixels, combined thickness of the color filter layer and the dynamic-range extending layer being uniform across the photosensitive pixel array.

Abstract: An image sensor pixel array comprises a plurality of image pixel units to gather image information and a plurality of phase detection auto-focus (PDAF) pixel units to gather phase information. Each of the PDAF pixel units includes two of first image sensor pixels covered by two micro-lenses, respectively. Each of the image pixel units includes four of second image sensor pixels adjacent to each other, wherein each of the second image sensor pixels is covered by an individual micro-lens. A coating layer is disposed on the micro-lenses and forms a flattened surface across the whole image sensor pixel array. A PDAF micro-lens is formed on the coating layer to cover the first image sensor pixels.

Abstract: A liquid-crystal display (LCD) system with reduced artifact has LCD pixel cells with transparent and pixel electrodes. A timing control that switches one of the transparent and pixel electrodes in a sequence of high, common, low, and common voltages; synchronized to a timing control that switches a second electrode in a sequence of a first data-dependent, common, a second data-dependent, and common voltages. This new timing base LC voltage control enables smooth polarity switching that prevents optical side effects by excessive voltage across LC.

Abstract: A method for determining exposure levels of an image-sensor pixel array includes (a) storing a first plurality of pixel values representing a first captured image, captured with the image sensor in an applied exposure configuration, each distinct region of the pixel array having a respective first exposure level, (b) determining pixel-value global statistics, (c) estimating, from the global statistics, a global pixel value of the first captured image, (d) determining, for each distinct region, a respective local statistics of the first pixel values, (e) assigning, to each distinct region, a respective scale factor based on the local statistics of the distinct region, (f) determining a refined exposure configuration including, for each distinct region, a second exposure level proportional to a product of its respective first exposure level and its respective scale factor, and (g) capturing second pixel values with the image sensor configured in the refined exposure configuration.

Abstract: Systems and methods for fixed pattern noise reduction in image sensors is disclosed herein. An example method may include simultaneously providing a pixel reference voltage of a pixel to a reference sampling capacitor and a signal sampling capacitor, decoupling the reference sampling capacitor from the pixel, providing a signal voltage to the signal sampling capacitor, and decoupling the signal sampling capacitor from the pixel.

Abstract: A first plasmonic-nanostructure sensor pixel includes a semiconductor substrate and a plurality of metal pillars. The semiconductor substrate has a top surface and a photodiode region therebeneath. The plurality of metal pillars is at least partially embedded in the substrate and extends from the top surface in a direction substantially perpendicular to the top surface. A second plasmonic-nanostructure sensor pixel includes (a) a semiconductor substrate having a top surface, (b) an oxide layer on the top surface, (c) a thin-film coating between the top surface and the oxide layer, and (d) a plurality of metal nanoparticles (i) at least partially between the top surface and the oxide layer and (ii) at least partially embedded in at least one of the thin-film coating and the oxide layer. A third plasmonic-nanostructure sensor pixel includes features of both the first and second plasmonic-nanostructure sensor pixels.

Abstract: A group of shared pixels comprises: a first shared pixel comprising a first photodiode and a first transfer gate; a second shared pixel comprising a second photodiode and a second transfer gate; a third shared pixel comprising a third photodiode and a third transfer gate; a fourth shared pixel comprising a fourth photodiode and a first transfer gate; a first floating diffusion shared by the first shared pixel and the second shared pixel; a second floating diffusion shared by the third shared pixel and the fourth shared pixel; a capacitor coupled to the first floating diffusion through a first dual conversion gain transistor, and the second floating diffusion through a second dual conversion gain transistor; wherein the capacitor is formed in an area covering most of the first shared pixel, the second shared pixel, the third shared pixel, and the fourth shared pixel.

Abstract: A group of shared pixels comprises: a first shared pixel comprising a first photodiode and a first transfer gate; a second shared pixel comprising a second photodiode and a second transfer gate; a third shared pixel comprising a third photodiode and a third transfer gate; a fourth shared pixel comprising a fourth photodiode and a first transfer gate; a first floating diffusion shared by the first shared pixel and the second shared pixel; a second floating diffusion shared by the third shared pixel and the fourth shared pixel; a capacitor coupled to the first floating diffusion through a first dual conversion gain transistor, and the second floating diffusion through a second dual conversion gain transistor; wherein the capacitor is formed in an area covering most of the first shared pixel, the second shared pixel, the third shared pixel, and the fourth shared pixel.

Abstract: A novel display system includes a host and a display. In a particular embodiment the host includes a data scaler and a dual frame buffer. Frames of image data are down-scaled before being transferred to the display, and is up-scaled while being loaded into the frame buffer or the display. The down-scaled frames of image data include less data than the frames of image data. In another embodiment, the process of loading the image data into the display begins before an entire frame of data is loaded into the frame buffer. Increasingly sized portions of the image data, each corresponding to a different color field, are asserted on the display and displayed one at a time. The portions of the frame that were not previously displayed are displayed along with the initial portions of a subsequent frame.

Abstract: An image sensor includes a substrate and a plurality of infrared pixels formed in a front side of the substrate and configured to detect infrared light incident on the front side of the substrate. Each of the infrared pixels includes a photodiode, a region free of implants located above the photodiode, and a photogate formed over the substrate and above the photodiode. The image sensor also includes a plurality of color pixels dispersed among the infrared pixels, where each of the color pixels includes a pinned photodiode and is configured to detect visible light. The photodiode of each of the infrared pixels can include a deep charge-accumulation region underlying the pinned photodiode(s) of one or more neighboring color pixel(s). Methods of manufacturing also described and include forming the deep charge-accumulation regions and associated elements prior to forming any implant-blocking elements (e.g., polysilicon photogates) over the substrate.

Abstract: An output circuit for use with a comparator includes a first transistor having a control terminal coupled to receive an output signal from a first stage of the comparator. A second transistor is coupled between the first transistor and a reference voltage. The second transistor has a control terminal coupled to receive a first reset signal. The second transistor is coupled to precharge a first output node of the first transistor between the first and second transistors to the reference voltage prior to a comparison operation of the comparator. An output stage has an input node coupled to the first output node. The output stage is coupled to generate an output voltage of the output circuit at an output node of the output stage in response to the first output node.

Abstract: A comparator includes a first stage coupled to compare a reference voltage to an image charge voltage signal. The first stage includes first and second NMOS input transistors coupled between an enabling transistor and respective first and second cascode devices to receive the reference voltage and the image charge voltage signal. A first auto-zero switch is between a gate of the first NMOS input transistor and a first node. The first node is between the first NMOS input transistor and the first cascode device. A second auto-zero switch is between a gate of the second NMOS input transistor and a second node. The second node is between the second cascode device and a second PMOS transistor. A voltage difference between the first and second nodes during an auto-zero period reduces an amount of kickback that occurs during an ADC period.