Abstract: A memory system includes a memory module and a memory controller to control semiconductor memory devices in the memory module. Each of the semiconductor memory devices provides the memory controller with an address of at least a defective memory cell row unrepairable with a redundancy resource in a memory cell array as unrepairable address information. The memory controller allocates a portion of a normal cell regions of at least one of the semiconductor memory devices as a reserved region, and remaps first and second unrepairable addresses to first and second physical addresses of the reserved region in response to first and second host physical addresses from a host matching the first and second unrepairable addresses, respectively. The first physical address and the second physical address are consecutive.

Abstract: A memory device includes a memory cell array, an address manager and a refresh controller. The memory cell array includes a plurality of memory cells coupled to a plurality of word-lines. The address manager samples access addresses provided from a memory controller to generate sampling addresses and determines a capture address from among the access addresses, based on a time interval between refresh commands from the memory controller. The refresh controller refreshes target memory cells from among the plurality of memory cells based on one of a maximum access address from among the sampling address and the captured address.

Abstract: A method includes receiving, at a controller of a computational storage (CS) device, a request to allocate computational storage to an application of a host device. The request includes a resource set ID associated with the application. The method further includes identifying a memory range within a memory region of the CS device. The method further includes storing, in a data structure associated with the resource set ID, an association between a memory range identifier (ID) of the memory range, the memory region, and an offset within the memory region. The method further includes sending the memory range ID to the host device.

Abstract: A memory device includes a memory cell array having a plurality of memory cells connected to wordlines and bitlines, a target row refresh logic configured to perform a refresh operation on at least one of target rows of the memory cell array in response to a refresh management mode command, a weak pattern detector that is activated according to a register update bit value included in the refresh management mode command and that outputs a risk level for each of the target rows, and a mode register circuit that updates at least one mode register value according to the risk level.

Abstract: A memory system includes a memory controller and a memory device including a plurality of dies, each die including a plurality of blocks. A plurality of commands are configured to control the memory device in units of super blocks. During a first time interval, a first erase operation is performed on a first-first block among the first-first block to a first-Mth block, and a first program operation is performed on a second-first block to a second-Mth block, based on the first commands. During a second time interval, a second erase operation is performed on a first-second block among the first-first block to the first-Mth block, and a second program operation is performed on the first-first block and one or more blocks among the second-first block to the second-Mth block, based on the second commands.

Abstract: A semiconductor device includes a memory cell array that includes a plurality of memory cells electrically connected to a plurality of word lines and a plurality of bit lines, a word line driving circuit that includes a plurality of sub-word line decoders electrically connected to the plurality of word lines, and a control logic configured to determine a selected word line and unselected word lines among the plurality of word lines, and configured to control the word line driving circuit such that at least one of the unselected word lines that is adjacent to the selected word line is floated during at least a portion of a period in which a voltage of the selected word line returns to an initial level.

Abstract: A storage device includes: a storage controller to receive one or more notifications corresponding to host data transferred from a host device to the storage device over a storage interface; and a response circuit connected to the storage controller, the response circuit to trigger a response to the host device, and including: a first counter to track the one or more notifications, the one or more notifications corresponding to an entirety of the host data such that each of the notifications corresponds to a portion of the host data; a second counter to track one or more acknowledgements received from the storage controller, the one or more acknowledgments corresponding to the one or more notifications such that each of the acknowledgments corresponds to a notification; and a response trigger to select one of the first counter and the second counter to trigger the response to the host device.

Abstract: In a sense amplifier circuit, a first transistor is electrically connected between a first bitline and a first node, a first inverter includes a first input terminal and a first output terminal connected to the first node, and a second inverter includes a second input terminal connected to a second node and a second output terminal. A second transistor is electrically connected between the first output terminal and the second node, and a third transistor is electrically connected between the second output terminal and the first node. A precharge circuit transfers a first voltage to the first and second nodes during a first period, and transfers a second voltage higher than the first voltage to the first and second nodes during a second period.

Abstract: A memory system includes a memory module and a memory controller. The memory module includes a control device, a module temperature sensor configured to measure a module temperature and a plurality of semiconductor memory devices configured to store data. The plurality of semiconductor memory devices respectively include a plurality of temperature measurement circuits configured to measure a plurality of internal temperatures respectively corresponding to the plurality of semiconductor memory devices. The memory system is configured to generate a reference offset value based on the module temperature and the plurality of internal temperatures and perform a thermal throttling of the memory module based on the reference offset value and the module temperature.

Abstract: A nonvolatile memory device includes a memory cell array having nonvolatile memory cells therein, which are electrically connected to a plurality of word lines and a plurality of bit lines. A write driver and row decoder are provided, which are electrically connected to the plurality of bit lines and the plurality of word lines, respectively. Control logic is configured to transfer a first voltage to the write driver and a second voltage to the row decoder. The control logic includes: (i) a normal standby mode circuit configured to operate in a normal standby mode, and (ii) a deep standby mode circuit configured to operate in a deep standby mode. To save power, the layout areas of a plurality of elements within the deep standby mode circuit are smaller than layout areas of elements within the normal standby mode circuit, so that current flowing within the deep standby mode circuit during the deep standby mode is less than current flowing within the normal standby mode circuit during the normal standby mode.

Abstract: The disclosure relates to a method, apparatus and device for sharing microservice application data. The method includes: managing, through data registration management, memory data registration information that is to be loaded by microservice application clusters; determining, according to the memory data registration information, memory data that are required by the microservice application clusters; partitioning and distributing the memory data to a plurality of memory computation service nodes in the microservice application clusters, and deploying the plurality of memory computation service nodes into a corresponding microservice application cluster at a proximal end; and loading the memory data in a preset manner in the plurality of memory computation service nodes, and sharing a corresponding memory computation service node in real time under the condition that the memory data change.

Abstract: A semiconductor device includes a memory device and a controller configured to perform an erase operation on the memory device, perform a correction operation for a threshold voltage of a deep-erased cell, and perform an erase verify operation by identifying whether threshold voltages of a plurality of cells of the memory device fall within a predefined range.

Abstract: A contactless information medium is provided with a spiral wiring on an IC chip. The IC chip has first and second electrodes, and the spiral wiring has first and second end portions electrically connected to the first and second electrodes, respectively. A first relay wiring is connected to the first electrode via a first connecting hole. The first end portion is connected to the first relay wiring via a third connecting hole formed on an inner peripheral side of the spiral wiring. The first relay wiring includes a rectangular region diagonally including the first connecting hole and the third connecting hole.

Abstract: A memory device, a memory system, and a program operation method are disclosed. In one example, at an ith programming loop, in response to determining that index i is greater than or equal to a first preset value and less than an initial verification loop number corresponding to a target state of memory cells in the memory device, an ith programming inhibition operation may be performed on the memory cells of the target state. Index i may be a positive integer, and the initial verification loop number may indicate a programming loop number that starts a verification operation corresponding to the target state of the memory cells.

Abstract: A method of deep neural network (DNN) modularization for optimal loading includes receiving, by an electronic device, a DNN model for execution, obtaining, by the electronic device, a plurality of parameters associated with the electronic device and a plurality of parameters associated with the DNN model, determining, by the electronic device, a number of sub-models of the DNN model and a splitting index, based on the obtained plurality of parameters associated with the electronic device and the obtained plurality of parameters associated with the DNN model, and splitting, by the electronic device, the received DNN model into a plurality of sub-models, based on the determined number of sub-models of the DNN model and the determined splitting index.

Abstract: A semiconductor device includes: a memory test circuit that outputs a fourth signal based on a logic level of a second signal corresponding to a first signal output by a host and a logic level of a third signal; a memory device that becomes active or inactive based on a logic level of the fourth signal; and a test logic that outputs the third signal and performs a retention test on the memory device based on the logic level of the second signal.

Abstract: A detection system of the present disclosure stores positions and the amount of game tokens that a game participant places on a game table based on a measurement result by a bet chip measuring device in the same persons for each game participant or player positions of the game table. A management control device compares an actual winning rate and a total return amount with figures obtained by a probability statistic calculation at the time of an end of the number of games to determine whether there is a significant difference therebetween and specifies any one of the game participant or the player position, the game table, or a room having the game table where the significant difference is occurring.

Abstract: A reference voltage generation device includes a noise information generation circuit configured to generate power noise information based on a first power noise and a second power noise, the first power noise and the second power noise generated based on a first power and a second power supplied to a first electronic device and propagated from the first electronic device to a second electronic device through a communication line, and the first electronic device and the second electronic device configured to perform data communication using a multi-level signaling scheme. The device includes a reference voltage generation circuit configured to generate three or more reference voltages for the multi-level signaling scheme based on the power noise information, and the second electronic device is configured to use the three or more reference voltages.

Abstract: Disclosed is a system and method for allowing one or more users to interact with models from a distance, for example, by enabling the users to input the models during online video chat sessions, wherein the models can define input parameters and provide at least one interactive interface, receive an interactive result according to the interactive interface to perform predefined acts, via an adult toy, based on the interactive result received. The adult toy can be Wi-Fi or Bluetooth™ enabled to receive commands directly from the server via a web browser extension, the website hosting an online video chat session, or connect to an application installed on a device operated by the model, wherein the application communicates with the web browser extension to relay commands to the adult toy therefrom. In some embodiments, the interactive interface provides a finger guessing game, a dice game or a lottery game.

Abstract: An operating method of a controller includes transmitting an extended status check command to a nonvolatile memory device, toggling a read activation signal /RE to correspond to the number of planes inside the nonvolatile memory device, after transmitting the extended status check command, and receiving status information of planes of the nonvolatile memory device through data lines according to a data strobe signal DQS corresponding to the read activation signal /RE.