Abstract: A display apparatus, an electronic apparatus, and an operating method thereof are provided.

Abstract: A device includes a fin on a substrate; a first transistor, including: a drain region and a first source region in the fin; and a first gate structure on the fin between the first source region and the drain region; a second transistor, including: the drain region and a second source region in the fin; and a second gate structure on the fin between the second source region and the drain region; a first resistor, including: the first source region and a first resistor region in the fin; and a third gate structure on the fin between the first source region and the first resistor region; and a second resistor, including: the second source region and a second resistor region in the fin; and a fourth gate structure on the fin between the second source region and the second resistor region.

Abstract: A pixel circuit and a display panel are provided. The pixel circuit includes a driving transistor T2 and a pulse width driving module. The pulse width driving module includes a display time control unit, an electrical potential modulation unit, and a Schmitt trigger. By connecting the Schmitt trigger in series between an output terminal of the electrical potential modulation unit and a control terminal of the display time control unit, the driving transistor T2 can be turned off more quickly, thereby accurately controlling the display time or light-emitting time of the pixel circuit.

Abstract: Semiconductor devices and methods are provided which facilitate performing physical failure analysis (PFA) testing from a backside of the devices. In at least one example, a device is provided that includes a semiconductor device layer including a plurality of diffusion regions. A first interconnection structure is disposed on a first side of the semiconductor device layer, and the first interconnection structure includes at least one electrical contact. A second interconnection structure is disposed on a second side of the semiconductor device layer, and the second interconnection structure includes a plurality of backside power rails. Each of the backside power rails at least partially overlaps a respective diffusion region of the plurality of diffusion regions and defines openings which expose portions of the respective diffusion region at the second side of the semiconductor device layer.

Abstract: Provided are a memory device for detecting a weakness of an operation pattern and a method of operating the same. The method includes: storing address information and activation count information regarding N word lines from among the plurality of word lines in a register including N entries; based on activation of a first word line different from the N word lines, storing address information and activation count information regarding the first word line in an entry from which information is evicted from among the N entries; and generating first weakness information based on a number of evictions performed on the register during a first period.

Abstract: A semiconductor module includes first and second semiconductor chips including first and second main electrodes, respectively; first and second connection terminals electrically connected to the first and second main electrodes, respectively; and an insulating sheet. The first connection terminal includes a first conductor portion including a first peripheral edge and a first terminal portion extending from the first peripheral edge in plan view, and the second connection terminal includes a second conductor portion including a second peripheral edge. A part of the first conductor portion overlap a part of the second conductor portion in plan view. The insulating sheet includes an insulating portion layered between the first and second conductor portions, and a first protruding portion positioned between a tip portion of the first terminal portion and the second peripheral edge in plan view, the first protruding portion forming an angle relative to a surface of the first terminal portion.

Abstract: A semiconductor memory device includes a command and address generator configured to decode a command to generate an active command, and generate an address applied with the active command as a row address, a control signal generator configured to generate sequence data changing with a random sequence in response to the active command, and generate a random pick signal when the sequence data is equal to previously stored comparison data, and a memory cell array comprising an odd page memory cell array including a plurality of first memory cells and an even page memory cell array including a plurality of second memory cells, and configured to simultaneously perform the active operation and a hidden hammer refresh operation on the selected first and second memory cells in response to the row address when the random pick signal is activated in response to the active command.

Abstract: A semiconductor package includes: a package substrate; an interposer disposed on the package substrate; a first semiconductor chip mounted on the interposer; a second semiconductor chip mounted on the interposer adjacent to the first semiconductor chip, the second semiconductor chip having an overhang portion that does not overlap the interposer in a vertical direction; a first underfill disposed between the package substrate and the interposer, the first underfill having a first extension portion extending from a side surface of the interposer; a second underfill disposed between the interposer and the second semiconductor chip, the second underfill having a second extension portion extending to an upper surface of the package substrate along at least a portion of the first extension portion of the first underfill, wherein the second extension portion protrudes from the overhang portion contact the upper surface of the package substrate.

Abstract: A memory device may include counters respectively corresponding to rows and each configured to count a number of accesses to a corresponding row, a refresh control circuit, a queue, and first flags respectively corresponding to the rows. The refresh control circuit may change a second flag set in a refresh period every refresh period, and determine whether to put an incoming row address into the queue based on a count value of a counter corresponding to a target row indicated by the incoming row address among the counters, a first flag value of a first flag corresponding to the target row among the first flags, and a second flag value of the second flag set in a current refresh period.

Abstract: A semiconductor device includes at least one first semiconductor element having a first electrode, a second semiconductor element having a second electrode, a first lead terminal connected to the first electrode of the at least one first semiconductor element, a second lead terminal connected to the second electrode of the second semiconductor element, a first resin with which the first lead terminal and the second lead terminal are sealed, and a second resin with which the at least one first semiconductor element and the second semiconductor element are sealed.

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cell rows, a row hammer management circuit and a control logic circuit. The row hammer management circuit stores counted values in count cells of each of the plurality of memory cell rows as count data based on an active command applied to the control logic circuit at a first time point, and performs an internal read-update-write operation to read the count data from the count cells of a target memory cell row from among the plurality of memory cell rows, to update the count data that was read to obtain updated count data, and to write the updated count data in the count cells of the target memory cell row in response to a precharge command applied at a second time point after a first command that is applied to the control logic circuit.

Abstract: A semiconductor package includes a redistribution substrate having first and second surfaces opposing one another, a first semiconductor chip on the first surface of the redistribution substrate, a passive device and a metal post on the second surface of the redistribution substrate and electrically connected to the redistribution pattern, a second encapsulant encapsulating at least side surfaces of the passive device and the metal post, a second insulating layer on a lower surface of the metal post and a lower surface of the second encapsulant, and having an opening exposing at least a portion of the lower surface of the metal post, and a connection bump filling the opening of the second insulating layer and in direct contact with the lower surface of the exposed metal post, wherein the metal post has a height greater than a height of each of the redistribution pattern and the redistribution via.

Abstract: Implementations provide a memory, a method for operating a memory, and a memory system. The discloses method can comprises: applying a multi-plane programming scheme to simultaneously perform programming operations on at least two memory planes of the memory device; and in response to determining that an exceptional memory plane of the at least two memory planes has a programming failure, switching to a single-plane programming scheme to sequentially perform programming operations on the at least two memory planes.

Abstract: Methods and systems for compressing a neural network (NN) which performs an inference task and for performing computations of a Kronecker layer of a Kronecker NN are described. Data samples are obtained from a training dataset. The input data of the data samples are inputted into a trained NN to generate NN predictions for the input data. Further, the input data are inputted into a Kronecker NN to generate Kronecker NN predictions for the input data. Two losses are computed: a knowledge distillation loss, based on outputs generated by a layer of the NN and a corresponding Kronecker layer of the Kronecker NN and a loss for Kronecker layer, based on the Kronecker NN predictions and ground-truth labels of the data samples. The two losses are combined into a total loss, which is propagated through the Kronecker NN to adjust values of learnable parameters of the Kronecker NN.

Abstract: A low-power memory device in which a NAND flash memory and a controller are connected to each other with a short wiring, the controller and a cache memory are connected to each other with a short wiring, and signal transmission delay is small is provided. For example, the NAND flash memory is formed using a Si transistor formed with a single crystal silicon substrate. Since an OS transistor can be formed by a method such as a thin-film method, the cache memory formed using the OS memory can be stacked over the NAND flash memory. When the NAND flash memory and the cache memory are formed in one chip, the NAND flash memory and the controller can be connected to each other with a short wiring, and the controller and the cache memory can be connected to each other with a short wiring.

Abstract: The present disclosure discloses a question analysis method, a device, a knowledge base question answering system and an electronic equipment. The method includes: analyzing a question to obtain N linearized sequences, N being an integer greater than 1; converting the N linearized sequences into N network topology maps; separately calculating a semantic matching degree of each of the N network topology maps to the question; and selecting a network topology map having a highest semantic matching degree to the question as a query graph of the question from the N network topology maps. According to the technology of the present disclosure, the query graph of the question can be obtained more accurately, and the accuracy of the question to the query graph is improved, thereby improving the accuracy of question analysis.

Abstract: A memory device and a programming method thereof are provided. The programming method includes the following steps. According to a step value, based on an incremental step pulse programming scheme, multiple programming operations are performed for a selected memory page. In a setting mode, multiple program verify operations are respectively performed corresponding to the programming operations to respectively generate multiple pass bit numbers. In the setting mode, a pass bit number difference value of two pass bit numbers corresponding to two programming operations is calculated. In the setting mode, an amount of the step value is adjusted according to the pass bit number difference value.

Abstract: A block packaging method based on blockchain transaction is used in an electronic device. The electronic device controls each node in the blockchain to receive and store a blockchain transaction, and calculate a hash value of the each node according to the blockchain transaction, generate a package voting information according to the hash value of the each node, and send the package voting information to a voted node. The electronic device further controls the each node to record the number of votes as the voted nodes according to the package voting information to obtain the number of votes of the each node, take the node with the largest number of votes as a target node according to the number of votes, and pack the blockchain transaction into blocks and broadcast the blocks to all nodes in the blockchain.

Abstract: A memory controller includes an error correction code (ECC) circuit configured to receive a data burst and generate first ECC data or second ECC data, and a processor configured to control operations of the ECC circuit. The ECC circuit includes an ECC select circuit configured to select and output one of first ECC conversion data and second ECC conversion data, based on an ECC select signal from outside the memory controller, and an ECC conversion circuit configured to generate the first ECC data by encoding the data burst, based on the first ECC conversion data, or generate the second ECC data by encoding the data burst, based on the second ECC conversion data. The second ECC conversion data is set to be capable of correcting an error generated in one or more preset protected bits among bits included in each of pieces of partial data included in the data burst.

Abstract: A student terminal is for viewing a class given in a virtual space that is immersive. The student terminal includes: a VR function section configured to display the virtual space according to virtual space information; and an input section for receiving a video capturing a desk of a student who views the class. The VR function section extracts, from the video, an area including a top plate of the desk corresponding to a desk object in the virtual space, and performs image composition for fitting a video capturing the area onto a top plate of the desk object.