Abstract: A method of forming a semiconductor device includes: forming a first conductive feature in a first dielectric layer disposed over a substrate; forming a second dielectric layer over the first dielectric layer; etching the second dielectric layer using a patterned mask layer to form an opening in the second dielectric layer, where the opening exposes the first conductive feature; performing an ashing process to remove the patterned mask layer after the etching; wet cleaning the opening after the ashing process, where the wet cleaning enlarges a bottom portion of the opening; and filling the opening with a first electrically conductive material.

Abstract: A first packet flow and a second packet flow support a first protocol, a third packet flow and a fourth packet flow support a second protocol, and a priority of the first protocol is lower than a priority of the second protocol. The first packet flow and the third packet flow are transmitted from a first ingress port to a first egress port. The second packet flow and the fourth packet flow are transmitted from a second ingress port to a second egress port. When the packet processing device is in a congested state, a bandwidth modulator performs a first suppression process on the first packet flow at the first ingress port, and the bandwidth modulator performs a second suppression process on the second packet flow at the second egress port or on the third packet flow at the first ingress port.

Abstract: An EUV lithographic apparatus includes a wafer stage and a particle removing assembly for cleaning a wafer for an extreme ultraviolet (EUV) lithographic apparatus. The wafer stage includes a measurement side and an exposure side. The particle removing assembly includes particle removing electrodes, an exhaust device and turbomolecular pumps. The particle removing electrodes is configured to direct debris from the chamber by suppressing turbulence such that the debris can be exhausted from the wafer stage to the outside of the processing apparatus. In some embodiments, turbomolecular pumps are turned off in the measurement side of the wafer stage so that an exhaust flow can be guided to an exposure side of the wafer stage. In some embodiments, the speed of voltage rise to the electrodes of the wafer chuck is adjusted.

Abstract: A touch display panel and an electronic terminal are disclosed in the present application, including a first conductive layer and a second conductive layer of different layers, and an insulation layer is arranged between the first conductive layer and the second conductive layer. The first conductive layer includes a plurality of touch electrodes arranged along a first direction and a second direction. The second conductive layer includes a first touch lead and a first auxiliary structure both overlapped with a first touch electrode in the plurality of touch electrodes. The first auxiliary structure is located on at least one side of the first touch lead.

Abstract: A package structure is provided. The package structure comprises a package substrate, an electronic device, a thermal interface material (TIM), a lid and an insulating encapsulant. The electronic device is disposed on and electrically connected to the package substrate. The TIM is disposed on the electronic device. The lid is disposed on the TIM. The insulating encapsulant is disposed on the package substrate and laterally encapsulates the electronic device and the TIM. A lateral dimension of the TIM is greater than a lateral dimension of the electronic device.

Abstract: A method for fabricating a semiconductor device is provided. The method includes forming a first memory cell and a second memory cell over a substrate, wherein each of the first and second memory cells comprises a bottom electrode, a resistance switching element over the bottom electrode, and a top electrode over the resistance switching element; depositing a first dielectric layer over the first and second memory cells, such that the first dielectric layer has a void between the first and second memory cells; depositing a second dielectric layer over the first dielectric layer; and forming a first conductive feature and a second conductive feature in the first and second dielectric layers and respectively connected with the top electrode of the first memory cell and the top electrode of the second memory cell.

Abstract: A semiconductor device is provided. The semiconductor device includes a silicon layer over a fin, a doped semiconductor layer over the fin and adjoining the silicon layer, a plurality of channel layers over the silicon layer, a source/drain structure on the doped semiconductor layer and adjoining plurality of channel layers, and a plurality of inner spacers between the plurality of channel layers.

Abstract: Provided is a pixel driving circuit connected to a light-emitting element, the pixel driving circuit including a first memory storing a bit value of bit data associated with image data of a single frame including a plurality of subframes, a controller configured to generate a pulse width modulation (PWM) signal and a control signal for controlling light emission or non-light emission of the light-emitting element, based on data stored in the first memory, a driving unit configured to supply power to the light-emitting element based on the PWM signal and the control signal, received from the controller, and a bias circuit configured to supply bias power to the driving unit based on the control signal received from the controller.

Abstract: A semiconductor device includes a semiconductor structure including a first conductive semiconductor layer, a second conductive semiconductor layer disposed on the first conductive semiconductor layer, and an active layer disposed between the first conductive semiconductor layer and the second conductive semiconductor layer. The first conductive semiconductor layer includes a first superlattice layer including a plurality of first sub layers and a plurality of second sub layers, and a first sub layer of the plurality of first sub layers and a second sub layer of the plurality of second sub layers are alternately disposed. The semiconductor structure includes a composition of a first dopant which is a n-type dopant.

Abstract: A wearable device is provided. The wearable device includes an electronic component and an encapsulant. The encapsulant includes a low-penetrability region encapsulating the electronic component and a high-penetrability region physically separated from the electronic component.

Abstract: A semiconductor device includes two source/drain regions, two isolation elements, a channel feature, at least one semiconductor layer and a gate feature. The source/drain regions are spaced apart from each other, and are respectively disposed above the isolation elements. The channel feature includes at least one effective channel layer and at least one dummy channel layer that are spaced apart from each other. Each of the at least one effective channel layer extends between the source/drain regions. Each of the at least one dummy channel layer extends between the isolation elements. The at least one semiconductor layer at least covers a lower surface of a bottommost one of the at least one dummy channel layer. The gate feature is disposed around the at least one effective channel layer, such that two opposite surfaces of each of the at least one effective channel layer are adjacent to the gate feature.

Abstract: A balun includes a first coil, a second coil, a third coil, a fourth coil, and a capacitor. The first coil is coupled between an unbalanced pin and a first ground terminal. The second coil is coupled between the first ground terminal and a second ground terminal. The third coil is coupled between a first balanced pin and a connection point and is inductively coupled to the first coil. The fourth coil is coupled between the connection point and a second balanced pin and is inductively coupled to the second coil. The capacitor is coupled between the connection point and a third ground terminal.

Abstract: A chip package structure is provided. The chip package structure includes a wiring structure. The chip package structure includes a first chip structure over the wiring structure. The chip package structure includes a first molding layer surrounding the first chip structure. The chip package structure includes a second chip structure over the first chip structure and the first molding layer. The chip package structure includes a second molding layer surrounding the second chip structure and over the first chip structure and the first molding layer. The chip package structure includes a third chip structure over the second chip structure and the second molding layer. The chip package structure includes a third molding layer surrounding the third chip structure and over the second chip structure and the second molding layer. The chip package structure includes a fourth molding layer surrounding the second molding layer and the third molding layer.

Abstract: A structure including a first semiconductor die, second semiconductor dies, a bridge die, and a gap filling material is provided. The first semiconductor die includes integrated circuit regions. The second semiconductor dies are disposed over and electrically connected to the first semiconductor die. The bridge die is disposed over and electrically connected to the first semiconductor die, and the integrated circuit regions are electrically connected to each other through the bridge die. The gap filling material is disposed on the first semiconductor die to laterally encapsulate the bridge die and the second semiconductor dies.

Abstract: The present disclosure provides a memory device including a substrate including a first and a second surfaces opposite to each other, a first interconnection structure disposed on the first surface of the substrate, a first and second elements disposed in the substrate and/or the first interconnection structure, a second interconnection structure disposed on the first interconnection structure, and a third interconnection structure disposed on the second surface of the substrate. The first interconnection structure includes first wiring layers configured to be closest to the first and second elements. The third interconnection structure includes second wiring layers configured to be closest to the first and second elements. Each of the first and second elements includes a first electrical connection path through the first wiring layer and a second electrical connection path through the second wiring layer.

Abstract: A light emitting apparatus is provided that includes a substrate, a light emitting device, a first light transmitting layer, and a first reflector. The light emitting device may be disposed on the substrate, and may emit light. The first light transmitting layer may be disposed on the substrate to cover the light emitting device, and may be formed of a material that transmit light emitted from the light emitting device. The first reflector may be disposed on at least a region of an upper surface of the first light transmitting layer, and may reflect at least a portion of light. In addition, the side surface of the first light transmitting layer includes an inclined surface.

Abstract: Disclosed is a semiconductor laser, from bottom to top, comprising: a substrate, a lower limiting layer, a lower waveguide layer, an active layer, an upper waveguide layer, and an upper limiting layer. The lower limiting layer is composed of at least one of AllnGaN, AllnN, AlGaN, InN, AlN, InGaN, and GaN. A thickness of the lower limiting layer is denoted as x, and 10 angstroms?x?90,000 angstroms. The lower limiting layer includes a first lower limiting layer, a second lower limiting layer, and a third lower limiting layer. The lower limiting layer forms an electron saving structure and a stress regulating structure to regulate a carrier distribution and a stress distribution of the active layer, thereby reducing a threshold current and improving a slope efficiency of the laser.

Abstract: A semiconductor apparatus and a method of manufacturing the same are provided. A semiconductor apparatus includes a first nitride semiconductor layer, a second nitride semiconductor layer, an electrode, a dielectric structure, a field plate, a plurality of height compensators, and a plurality of vias. The second nitride semiconductor layer is on the first nitride semiconductor layer and has a bandgap greater than that of the first nitride semiconductor layer. The electrode contacts the second nitride semiconductor layer. The dielectric structure is disposed on the second nitride semiconductor layer and covers the electrode. The field plate is in the dielectric structure. The height compensators are in the dielectric structure and are disposed on the electrode and the field plate, respectively. The vias extend into the dielectric structure and contact top surfaces of the height compensators, respectively.

Abstract: A method for operating a memory device is provided. A first address is decoded to select a bit line of a memory device. A second address is decoded to select a word line of the memory device. A word line voltage is applied to the selected word line. A bit line voltage is applied to the selected bit line. A first bias voltage is applied to each of a plurality of unselected word lines connected to a plurality of memory cells connected to the selected bit line san a memory cell connected to both the selected bit line and the selected word line.

Abstract: A semiconductor device includes a channel structure, source region, a drain region, metal gate structure, and a self-assembled layer. The source region and the drain region are on opposite sides of the channel structure. A bottom surface of the source region is lower than a bottom surface of the channel structure, and a top surface of the source region is higher than a top surface of the channel structure. The metal gate structure covers the channel structure and between the source region and the drain region. The self-assembled layer is between the source region and the metal gate structure. The self-assembled layer is in contact with the bottom surface of the channel structure but spaced apart from the top surface of the channel structure.