Abstract: Encoding devices, methods and programs that encode with high transmission efficiency by controlling a running disparity are disclosed. In one example, an encoding device includes a scrambling circuit that scrambles an input data string, a calculation circuit that calculates a first running disparity of the scrambled data string, a determination circuit that determines whether or not to invert the scrambled data string on the basis of a first running disparity calculated by the calculation circuit and a second running disparity calculated at a time point before the first running disparity, and an addition circuit that inverts or non-inverts the scrambled data string on the basis of a determination result by the determination circuit, adds a flag indicating the determination result, and outputs the data string. The technology can be applied to devices that perform SLVS-EC standard communication.

Abstract: A light-emitting device includes a lead frame having a first surface on which a patterned conductive layer is provided, and a light-emitting element. The light-emitting element includes an insulating substrate formed on the first surface, a plurality of light-emitting units formed on the insulating substrate, at least one first electrode, at least one second electrode and at least a pair of bonding wires. The first and second electrodes are respectively placed in electrical connection with a first one and a second one of the light-emitting units, and are disposed outward of the light-emitting units. Each of the pair of bonding wires is disposed to electrically connect a respective one of the first and second electrodes to the patterned conductive layer.

Abstract: The present application provides a method for forming chip packages and a chip package. The method comprises arranging a plurality of interconnect devices at intervals on a surface of a carrier and assembling a plurality of chipsets over the interconnect devices. Each chipset comprises at least two chips electrically connected through an interconnect device. A front surface of each chip facing the carrier is provided with a plurality of first bumps. The method further comprises forming a molded package layer whereby the plurality of chipsets and the plurality of interconnect devices are embedded in the molded package layer; removing the carrier and thinning the molded package layer to expose the first bumps; forming second bumps on the surface on one side of the molded package layer where the first bumps are exposed; and dicing the molded package layer to obtain a plurality of package units. Thus, a flexible and low-cost packaging scheme is provided for multi-chip interconnection.

Abstract: The present application is applicable to the field of semiconductor technology and provides a method for packaging stacking a flip chip, which includes: placing a filling template on a substrate, the filling template being provided with a through hole of a preset pattern; filling a filling material into the through hole of the filling template, and after the filling material being formed on the substrate, removing the filling template; placing a chip with solder balls on the substrate formed with the filling material, such that at least a portion of the solder balls being covered by the filling material; and connecting the chip to the substrate through the solder balls, and curing the filling material with air gaps formed between the at least a portion of the solder balls covered with the filling material.

Abstract: A light-emitting device with high emission efficiency and reliability is provided. The light-emitting device includes first and second fluorescent light-emitting layers. A host material used in the first fluorescent light-emitting layer has a function of converting triplet excitation energy into light emission, a guest material used in the first light-emitting layer has a molecular structure including a luminophore and a protecting group, and one molecule of the guest material includes five or more protecting groups. The introduction of the protecting groups into the molecule inhibits transfer of triplet excitation energy by the Dexter mechanism from the host material to the guest material. An alkyl group or a branched-chain alkyl group is used as the protecting groups. The materials are selected such that the triplet excitation energy level of the host material in the second light-emitting layer is lower than the triplet excitation energy level of the guest material in the second light-emitting layer.

Abstract: Some embodiments provide a three-dimensional (3D) circuit that has data lines of one or more memory circuits on a different IC die than the IC die(s) on which the memory blocks of the memory circuit(s) are defined. In some embodiments, the 3D circuit includes a first IC die with a first set of two or more memory blocks that have a first set of data lines. The 3D circuit also includes a second IC die that is stacked with the first IC dies and that includes a second set of two or more memory blocks with a second set of data lines. The 3D circuit further includes a third IC die that is stacked with the first and second IC dies and that includes a third set of data lines, which connect through several z-axis connections with the first and second sets of data lines to carry data to and from the first and second memory block sets when data is being written to and read from the first and second memory block sets.

Abstract: A method includes forming a dummy gate stack on a semiconductor fin, forming gate spacers on sidewalls of the dummy gate stack, forming a first inter-layer dielectric, with the gate spacers and the dummy gate stack being in the first inter-layer dielectric, removing the dummy gate stack to form a trench between the gate spacers, forming a replacement gate stack in the trench, and depositing a dielectric capping layer. A bottom surface of the dielectric capping layer contacts a first top surface of the replacement gate stack and a second top surface of the first inter-layer dielectric. A second inter-layer dielectric is deposited over the dielectric capping layer. A source/drain contact plug is formed and extends into the second inter-layer dielectric, the dielectric capping layer, and the first inter-layer dielectric.

Abstract: Disclosed are a pixel compensation circuit, a drive method thereof, and a display panel. The pixel compensation circuit includes a drive transistor, a data write module, a first initialization module, a second initialization module, a storage capacitor, and a light-emitting device. The drive timing of the pixel compensation circuit includes a threshold voltage compensation stage in which a detected threshold voltage of the drive transistor is less than an actual threshold voltage of the drive transistor.

Abstract: In an embodiment a method for producing a component having a carrier and at least one component part electrically conductively connected to the carrier and mechanically fixed to the carrier by an electrically insulating bonding layer includes providing the carrier having a connection layer, wherein the bonding layer is disposed on the carrier and has at least one opening, wherein a connection surface of the connection layer is exposed, and wherein the bonding layer projects vertically beyond the exposed connection surface or vice versa, applying the component part having a contact layer on the carrier in such that, in top view of the carrier, an exposed contact surface of the contact layer covers the opening and the connection surface located therein, wherein the exposed contact surface is spaced apart from the exposed connection surface by a vertical distance and reducing the vertical distance by changing a volume of the bonding layer such that the exposed contact surface and the exposed connection surface a

Abstract: A display panel and a display device are provided. An adhesive layer is disposed between an organic layer and an inorganic layer in a bonding area of the display panel, where a surface roughness of an adhesive layer material is greater than a surface roughness of an organic layer material and a surface roughness of an inorganic layer material. In addition, a plurality of concave-convex structures can be provided on a surface of the organic layer and/or a surface of the inorganic layer in contact with the adhesive layer to enhance interface bonding force. This can alleviate a problem that film layers are prone to peeling off when a flexible printed circuit (FPC) is bonded to the display panel in the prior art.

Abstract: A semiconductor structure includes a semiconductor substrate, a semiconductor device and a heating structure. The semiconductor substrate includes a device region and a heating region surrounding the device region. The semiconductor device is located on the device region. The heating structure is located on the heating region and includes an intrinsic semiconductor area, at least one heating element and at least one heating pad. The intrinsic semiconductor area is surrounding the semiconductor device. The at least one heating element is located at a periphery of the intrinsic semiconductor area. The at least one heating pad is joined with the at least one heating element, wherein the at least one heating pad includes a plurality of contact structures, and a voltage is supplied from the plurality of contact structures to control a temperature of the at least one heating element.

Abstract: A method of manufacturing a semiconductor device includes at least the following steps. A protrusion is formed in a substrate by an anisotropic etch process, wherein a sidewall of the protrusion is inclined. A recess is formed on the sidewall of the protrusion by an isotropic etch process, wherein during the isotropic etch process, a by-product covers a first portion of the sidewall of the protrusion while exposing a second portion of the sidewall of the protrusion, so that the recess is formed between the first portion and the second portion of the sidewall.

Abstract: A device includes a diffraction-based overlay (DBO) mark having an upper-layer pattern disposed over a lower-layer pattern, and having smallest dimension greater than about 5 micrometers. The device further includes a calibration mark having an upper-layer pattern disposed over a lower-layer pattern, positioned substantially at a center of the DBO mark, and having smallest dimension less than about ? the size of the smallest dimension of the DBO mark.

Abstract: A light-emitting diode chip includes a substrate. The substrate has a side surface configured as a serrated surface, which includes a plurality of laser inscribed features disposed along a thickness direction of the substrate and spaced apart from each other. A method for manufacturing the light-emitting diode chip is also disclosed herein.

Abstract: A waterproof-state recognition and processing method and device is applicable to a capacitive touch screen. The method and device can differentiate a water-affected region from a water-free region, and allow a touch-responding operation for the water-free region when the water-affected region exists. The method includes: scanning the screen to obtain data of multiple channels of the screen; determining whether any of the data reaches a waterproof threshold; when any of the data reaches the waterproof threshold, performing a waterproof-state process; when none of the data reaches the waterproof threshold, determining whether any of the data reaches a finger-touch threshold; when any of the data reaches the finger-touch threshold, performing a finger-touch-state process; and when none of the data reaches the finger-touch threshold, performing an idle-state process.

Abstract: A splicing assembly and a splicing display screen are disclosed. A first adjustment module includes a first support block and a first support pillar. The first support block is slidably connected to a support frame along a first direction. The first support pillar passes through the first support block and a connecting plate in sequence along a second direction. The first support pillar is screwed with the first support block, and the connecting plate is hung on the first support pillar. An adjusting part passes through the connecting plate along a third direction and abuts against the first support pillar, and the adjusting part is screwed with the connecting plate.

Abstract: The present disclosure relates to a resistive random access memory (RRAM) device. In some embodiments, the RRAM device includes a first electrode disposed over a substrate and a second electrode over the first electrode. A doped data storage structure is disposed between the first electrode and the second electrode. The doped data storage structure has a dopant with a doping concentration profile that is asymmetric over a height of the doped data storage structure and that has a maximum dopant concentration at non-zero distances from a top surface and a bottom surface of the doped data storage structure.

Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate, a first dielectric layer, an etching stop layer, a second dielectric layer, a conductive via, and a data storage structure. The first dielectric layer is disposed on the substrate. The etching stop layer is disposed on the first dielectric layer. The second dielectric layer is disposed on the etching stop layer. The first dielectric layer, the etching stop layer, and the second dielectric layer collectively define an opening. The conductive via is disposed in the opening. The data storage structure is disposed on the conductive via.

Abstract: A device and a method of making the device comprising, a semiconductor substrate layer and an epitaxial layer formed on the semiconductor substrate. One or more trenches are formed in the epitaxial layer, each trench having a pair of opposing sidewalls, wherein a distance between the opposing sidewalls is greater near a bottom of the trench than near a top of the trench, wherein the bottom of the trench is closer to the semiconductor substrate layer than the top.

Abstract: A method of operating a memory circuit includes turning on a first programming device and turning on a first selection device thereby causing a first current to flow through a first fuse element. The first fuse element is coupled between the first selection device and the first programming device. The method further includes turning off a second programming device and turning off a second selection device, and blocking the first current from flowing through a second fuse element that is coupled between the second selection device and the first programming device.