Abstract: Double patterning techniques described herein may reduce corner rounding, etch loading, and/or other defects that might otherwise arise during formation of a deep trench isolation (DTI) structure in a pixel array. The double patterning techniques include forming a first set of trenches in a first direction and forming a second set of trenches in a second direction in a plurality of patterning operations such that minimal to no etch loading and/or corner rounding is present at and/or near the intersections of the first set of trenches and the second set of trenches.

Abstract: The invention provides a flexible display panel and a flexible display device. The flexible display panel includes: a substrate, an auxiliary cathode provided on the substrate, an separation layer disposed on the substrate and the auxiliary cathode and defining a first opening to expose the auxiliary cathode, a passivation layer disposed on the separation layer and extending into the first opening as an undercut structure, an auxiliary anode arranged in the first opening and connected to the auxiliary cathode, and a cathode layer arranged on the auxiliary anode with a left end and a right end respectively connected with the auxiliary anode.

Abstract: A quinoxaline derivative that is a novel organic compound is provided. A quinoxaline derivative represented by General Formula (G1) has a structure in which a quinoxaline skeleton is bonded to the 9-position of an anthracene skeleton, the 10-position of the anthracene skeleton is bonded to a heteroaromatic ring, and the 3-position of the heteroaromatic ring is nitrogen. In General Formula (G1) shown above, a and b each independently represent a substituted or unsubstituted arylene group having 6 to 13 carbon atoms in a ring. In addition, m and n are each independently 0, 1, or 2.

Abstract: A method is provided including forming a first layer over a substrate and forming an adhesion layer over the first layer. The adhesion layer has a composition including an epoxy group. A photoresist layer is formed directly on the adhesion layer. A portion of the photoresist layer is exposed to a radiation source. The composition of the adhesion layer and the exposed portion of the photoresist layer cross-link using the epoxy group. Thee photoresist layer is then developed (e.g., by a negative tone developer) to form a photoresist pattern feature, which may overlie the formed cross-linked region.

Abstract: Embodiments of the present disclosure disclose a touch display panel, which includes a plurality of touch sub-units and a plurality of connection wires, wherein the plurality of touch sub-units include the touch sub-units extending in a first direction and a second direction, and two adjacent columns of the touch sub-units extending in the second direction are electrically connected via connection wires; in one of touch electrode repetition units, the connection wires distributed in the first direction are disposed in a misaligned manner in the second direction.

Abstract: A method for system profiling and controlling and a computer system performing the same are provided. In the method, an operating system is operated after the computer system is booted, in which a profiling-controlling system is operated. When the operating system loads and executes a system profiling-controlling program, the profiling-controlling system that simultaneously operates a profiling routine and a controlling routine is initiated. The profiling routine is used to retrieve system kernel data that is generated during operation of the operating system and analyze the system kernel data through a kernel tracing tool. When it is determined that controlling is required, the profiling routine notifies the controlling routine. The controlling routine controls operating parameters of the operating system in real time according to an analysis result generated by the profiling routine.

Abstract: A semiconductor package includes a semiconductor die and a redistribution structure. The semiconductor die is laterally surrounded by a molding compound, and the semiconductor die has a conductive pillar and a complex compound sheath sandwiched between the conductive pillar and the molding compound. The redistribution structure is electrically connected with the semiconductor die and comprises a first via portion at a first side of the redistribution structure and a second via portion at a second side of the redistribution structure, and a base angle of the second via portion is greater than a base angle of the first via portion.

Abstract: The present application provides a gate driving circuit and a display device including a pull-up module, an isolation module, a pull-down maintaining module, and an inverting module. A coupling effect of an electric potential variation of a first node on an electric potential of a second node is blocked by providing the isolation module. Therefore, in a case that a clock signal fluctuates so that the electric potential of the first node fluctuates, that a change of the electric potential of the first node spreads to the electric potential of the second node is blocked, and the electric potential of the second node is stabilized. A failure of the gate driving circuit is improved.

Abstract: A wedge amplitude-modulation probe card and a main body thereof. The probe card includes a probe card main body, upper wedge plates and lower wedge plates. Several upper wedge plates and several lower wedge plates are slidably arranged inside the probe card main body, and the several upper wedge plates and the several lower wedge plates are sequentially arranged at intervals in a staggered manner, so that by means of inserting different numbers of upper wedge plates between the lower wedge plates, probes on the upper wedge plates can be inserted into or shifted out of a probe queue thereunder, so as to increase or decrease the number of probes for testing, and thus, the testing amplitude of a single probe card can be adjusted, such that the probe card has universality.

Abstract: A method of forming a semiconductor device includes forming a conductive line over a substrate; forming an etch stop layer (ESL) over the conductive line, the ESL extending continuously along an upper surface of the conductive line and along an upper surface of a first dielectric layer adjacent to the conductive line, where a first lower surface of the ESL contacts the upper surface of the conductive line, and a second lower surface of the ESL contacts the upper surface of the first dielectric layer, the first lower surface being closer to the substrate than the second lower surface; forming a second dielectric layer over the ESL; forming an opening in the second dielectric layer, the opening exposing a first portion of the ESL; removing the first portion of the ESL to expose the conductive line; and filling the opening with an electrically conductive material to form a via.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate and a metallization layer. The metallization layer is disposed over the substrate. The metallization layer includes a first signal line, a second signal line, and a third signal line, wherein the first signal line, the second signal line, and the third signal line are arranged in a first row between a power rail and a ground rail parallel to the power rail. A first distance between the first signal line and the second signal line is different from a second distance between the second signal line and the third signal line. A method for manufacturing a semiconductor structure is also provided.

Abstract: A semiconductor structure includes a substrate including a first surface; a dielectric layer disposed over the first surface of the substrate; a first conductive line surrounded by the dielectric layer and extended over the first surface of the substrate; a second conductive line disposed adjacent to the first conductive line, surrounded by the dielectric layer and extended parallel to the first conductive line; a conductive via disposed over the first conductive line and extended through the dielectric layer; and a cross section of the conductive via substantially parallel to the first surface of the substrate, wherein the cross section of the conductive via is at least partially protruded from the first conductive line towards the second conductive line. Further, a method of manufacturing the semiconductor structure is also disclosed.

Abstract: A circuit for parameter PSRR measurement includes a filter, a first regulator and a second regulator. The filter may be configured for receiving an AC input signal and a DC input signal, and for outputting a combined output signal according to the AC input signal and the DC input signal. The first regulator may be configured for receiving the combined output signal, and for outputting a first output signal having a first AC component signal and a first DC component signal. The second regulator may be configured for receiving the first output signal, and for outputting a second output signal having a second AC component signal and a second DC component signal. A parameter PSRR of the second regulator may be obtained according to a ratio between the second AC component signal and the first AC component signal.

Abstract: A package structure is provided. The package structure includes a substrate, a cover element, a semiconductor device, a protruding element, an adhesive element, and an electrical connector. The cover element is disposed on the substrate and having a recess. The semiconductor device is disposed on the substrate and disposed in the space surrounded by the cover element. The protruding element extends from the substrate and disposed in the recess. The adhesive element is disposed in the recess. The electrical connector is in contact with the substrate and the semiconductor device.

Abstract: Provided is a solid-state imaging element capable of thinning out the number of operations of AD conversion units while suppressing an influence of a noise component on the AD conversion units of other columns.

Abstract: A method may include forming a mask layer on top of a first dielectric layer formed on a first source/drain and a second source/drain, and creating an opening in the mask layer and the first dielectric layer that exposes portions of the first source/drain and the second source/drain. The method may include filling the opening with a metal layer that covers the exposed portions of the first source/drain and the second source/drain, and forming a gap in the metal layer to create a first metal contact and a second metal contact. The first metal contact may electrically couple to the first source/drain and the second metal contact may electrically couple to the second source/drain. The gap may separate the first metal contact from the second metal contact by less than nineteen nanometers.

Abstract: An integrated circuit package integrates a photonic die (oDie) and an electronic die (eDie). More specifically, the integrated circuit package may include a plurality of redistribution layers communicatively coupled to at least one of the oDie and/or the eDie, where molded material at least partially surrounds the at least one of the oDie and/or the eDie.

Abstract: An integrated circuit (IC) with through-circuit vias (TCVs) and methods of forming the same are disclosed. The IC includes a semiconductor device, first and second interconnect structures disposed on first and second surfaces of the semiconductor device, respectively, first and second inter-layer dielectric (ILD) layers disposed on front and back surfaces of the substrate, respectively, and a TCV disposed within the first and second interconnect structures, the first and second ILD layers, and the substrate. The TCV is spaced apart from the semiconductor device by a portion of the substrate and portions of the first and second ILD layers. A first end of the TCV, disposed over the front surface of the substrate, is connected to a conductive line of the first interconnect structure and a second end of the TCV, disposed over the back surface of the substrate, is connected to a conductive line of the second interconnect structure.

Abstract: A semiconductor die includes an array of first capacitor regions, each of the first capacitor regions including multiple first capacitor cell structures, wherein each first capacitor cell structure includes a plurality of first trench segments characterized by a first trench length, a first trench width, and a first trench spacing, and a first air gap width in a gap-filling material. The semiconductor die also includes a plurality of second capacitor regions interspersed in the array of first capacitor regions, each of the second capacitor region including multiple second capacitor cell structures, wherein each second capacitor cell structures includes a plurality of second trench segments characterized by a second trench length, a second trench width, a second trench spacing, and a second air gap width in the gap-filling material.

Abstract: A display panel and a display device are provided by the present application. A first part and a second part of part of a first scanning signal line are connected through a third part, and/or a fourth part and a fifth part of part of the first scanning signal line are connected through a sixth part, so that a load of a hole-digging area is similar or even consistent with a load of other areas, thereby improving a display effect.