Abstract: An infrared thermal emitter includes a substrate, a light-emitting unit and an infrared-emitting unit. The light-emitting unit is disposed on the substrate in a laminating direction and has a light-exiting surface away from the substrate. The infrared-emitting unit is disposed on the substrate in the laminating direction to cover the light-emitting unit and includes a layered structure having a light-absorbing layer that is aligned with the light-emitting unit in the laminating direction. The light-absorbing layer absorbs light emitted from the light-emitting unit so as to be heated up and to generate infrared radiation.

Abstract: A top-emitting light-emitting diode includes a glass substrate, a polysilicon layer, a white light emitting layer and a transparent conductive layer. The polysilicon layer is formed on a first surface of the glass substrate. Moreover, plural sub-wavelength structures are discretely arranged on a surface of the polysilicon layer at regular intervals. The white light emitting layer is formed over the polysilicon layer and the plural sub-wavelength structures. The transparent conductive layer is formed over the white light emitting layer.

Abstract: An infrared thermal emitter includes a substrate, a light-emitting unit and an infrared-emitting unit. The light-emitting unit is disposed on the substrate in a laminating direction and has a light-exiting surface away from the substrate. The infrared-emitting unit is disposed on the substrate in the laminating direction to cover the light-emitting unit and includes a layered structure having a light-absorbing layer that is aligned with the light-emitting unit in the laminating direction. The light-absorbing layer absorbs light emitted from the light-emitting unit so as to be heated up and to generate infrared radiation.

Abstract: A light emitting diode memory includes a substrate, a tunneling structure, a current spreading layer, a first electrode layer and a second electrode layer. The tunneling structure is formed on the substrate. The tunneling structure includes first, second and third material layers. The current spreading layer is formed on the tunneling structure. The first electrode layer is formed on the substrate. The second electrode layer is formed on the current spreading layer. When a bias voltage applied to the first electrode layer and the second electrode layer is higher than a reset voltage, the light emitting diode memory is in a reset state. When the bias voltage is lower than a set voltage, the light emitting diode memory is in a set state. When the bias voltage is higher than a turn-on voltage, the light emitting diode memory emits a light beam.

Abstract: The present invention relates to a light-emitting apparatus, which comprises at least one reflective housing, at least one light-emitting module, and a reflective member. The reflective housing includes a housing body and a curved surface part. The curved surface part is located on the housing body. The light-emitting module is located below the reflective housing. The light-emitting module includes a light guide plate and at least one light-emitting device. The light-emitting device is located on one side of the light guide plate. The light guide plate includes a plate body and a hole. The hole corresponds to an opening on the curved surface part and is located on the plate body. The reflective member is located below the light-emitting module. The reflective member includes a body and a light-emitting hole. The light-emitting hole corresponds to the hole and located on the body.

Abstract: The present invention relates to a lamp structure, which comprises a light guide plate, a lamp plate, and a lamp housing. The light guide plate includes an inner loop, an outer loop, and an annular tortuous structure. The annular tortuous structure includes a plurality of top recesses and a plurality of bottom recesses. The plurality of top recesses and the plurality of bottom recesses are interlaced to give a continuous concave-convex structure. The lamp plate is disposed inside the inner loop. The lamp housing includes a top housing member and a bottom housing member. The top and bottom housing members are located on both sides of the lamp plate and disposed on the two loop openings of the inner loop and opposing to each other. Thereby, the light of the lamp plate illuminates outward via the shape and structure of the light guide plate.

Abstract: A resistive memory element includes a P-type layer, a tunneling structure and an N-type layer. The tunneling structure is formed on the P-type layer. The N-type layer is formed on the tunneling structure. When a bias voltage higher than a reset voltage is applied to the P-type layer and the N-type layer, the resistive memory element is in a reset state. When the bias voltage lower than a set voltage is applied to the P-type layer and the N-type layer, the resistive memory element is in a set state.

Abstract: A substrate with a lithium imide layer, a LED with a lithium imide layer and a manufacturing method of the LED are provided. The substrate includes a lithium niobate layer and a lithium imide layer. The lithium imide layer is formed on a surface of the lithium niobate layer.

Abstract: A white LED chip includes a P-type layer, a tunneling structure, an N-type layer, an N-type electrode, and a P-type electrode. The tunneling structure is disposed over the P-type layer. The tunneling structure includes a first barrier layer, an active layer and a second barrier layer. The first barrier layer includes a first material layer, the active layer includes a second material layer, and the second barrier layer includes a third material layer. The N-type layer is disposed over the tunneling structure. An energy gap of the second material layer is lower than an energy gap of the first material layer and an energy gap of the third material layer. Each of the first material layer, the second material layer and the third material layer is a metal oxide layer, a metal nitride layer or a metal oxynitride layer.

Abstract: A single memory cell has the functions of a storage element and a selector. The memory cell includes a P-type layer, a tunneling structure and an N-type layer. The tunneling structure is formed on the P-type layer. The N-type layer is formed on the tunneling structure. The tunneling structure is a stack structure including a first material layer, a second material layer and a third material layer. By adjusting a bias voltage that is applied to the P-type layer and the N-type layer, the tunneling structure is controlled to be in the amorphous state or the crystalline state. Consequently, the memory cell has the memorizing and storing functions. The memory cell has the P-type layer, the tunneling structure and the N-type layer. By adjusting the bias voltage, the function of the selector is achieved.

Abstract: A white LED includes a P-type layer, a tunneling structure, an N-type layer, an N-type electrode, and a P-type electrode. The tunneling structure is in contact with the P-type layer. The tunneling structure is a stack structure comprising a first barrier layer, a first active layer and a second barrier layer. At least one of the first barrier layer, the first active layer and the second barrier layer is a first metal nitride oxide layer. The N-type layer is in contact with the tunneling structure. The N-type electrode is in contact with the N-type layer. The P-type electrode is in contact with the P-type layer.

Abstract: A white LED is provided. The white LED includes a P-type layer, a tunneling structure, an N-type layer, an N-type electrode, and a P-type electrode. The tunneling structure is disposed over the P-type layer. The tunneling structure includes a first barrier layer, an active layer and a second barrier layer. The first barrier layer includes a first metal oxide layer. The active layer includes a second metal oxide layer. The second barrier layer includes a third metal oxide layer. The N-type layer is disposed over the tunneling structure. The N-type electrode and the P-type electrode are respectively contacted with the N-type layer and the P-type layer. An energy gap of the second metal oxide layer is lower than an energy gap of the first metal oxide layer and is lower than an energy gap of the third metal oxide layer.

Abstract: A white LED is provided. The white LED includes a P-type layer, a tunneling structure, an N-type layer, an N-type electrode, and a P-type electrode. The tunneling structure is disposed over the P-type layer. The tunneling structure includes a first barrier layer, an active layer and a second barrier layer. The first barrier layer includes a first metal oxide layer. The active layer includes a second metal oxide layer. The second barrier layer includes a third metal oxide layer. The N-type layer is disposed over the tunneling structure. The N-type electrode and the P-type electrode are respectively contacted with the N-type layer and the P-type layer. An energy gap of the second metal oxide layer is lower than an energy gap of the first metal oxide layer and is lower than an energy gap of the third metal oxide layer.

Abstract: Various embodiments of the present disclosure pertain to selective photo-enhanced wet oxidation for nitride layer regrowth on substrates. In one aspect, a method may comprise: forming a first III-nitride layer with a first low bandgap energy on a first surface of a substrate; forming a second III-nitride layer with a first high bandgap energy on the first III-nitride layer; transforming portions of the first III-nitride layer into a plurality of III-oxide stripes by photo-enhanced wet oxidation; forming a plurality of III-nitride nanowires with a second low bandgap energy on the second III-nitride layer between the III-oxide stripes; and selectively transforming at least some of the III-nitride nanowires into III-oxide nanowires by selective photo-enhanced oxidation.

Abstract: Various embodiments of the present disclosure pertain to selective photo-enhanced wet oxidation for nitride layer regrowth on substrates. In one aspect, a method may comprise: forming a first III-nitride layer with a first low bandgap energy on a first surface of a substrate; forming a second III-nitride layer with a first high bandgap energy on the first III-nitride layer; transforming portions of the first III-nitride layer into a plurality of III-oxide stripes by photo-enhanced wet oxidation; forming a plurality of III-nitride nanowires with a second low bandgap energy on the second III-nitride layer between the III-oxide stripes; and selectively transforming at least some of the III-nitride nanowires into III-oxide nanowires by selective photo-enhanced oxidation.

Abstract: Various embodiments of the present disclosure pertain to selective photo-enhanced wet oxidation for nitride layer regrowth on substrates. In one aspect, a method may comprise: forming a first III-nitride layer with a first low bandgap energy on a first surface of a substrate; forming a second III-nitride layer with a first high bandgap energy on the first III-nitride layer; transforming portions of the first III-nitride layer into a plurality of III-oxide stripes by photo-enhanced wet oxidation; forming a plurality of III-nitride nanowires with a second low bandgap energy on the second III-nitride layer between the III-oxide stripes; and selectively transforming at least some of the III-nitride nanowires into III-oxide nanowires by selective photo-enhanced oxidation.

Abstract: Various embodiments of the present disclosure pertain to selective photo-enhanced wet oxidation for nitride layer regrowth on substrates. In one aspect, a method may comprise: forming a first III-nitride layer with a first low bandgap energy on a first surface of a substrate; forming a second III-nitride layer with a first high bandgap energy on the first III-nitride layer; transforming portions of the first III-nitride layer into a plurality of III-oxide stripes by photo-enhanced wet oxidation; forming a plurality of III-nitride nanowires with a second low bandgap energy on the second III-nitride layer between the III-oxide stripes; and selectively transforming at least some of the III-nitride nanowires into III-oxide nanowires by selective photo-enhanced oxidation.

Abstract: Various embodiments of the present disclosure pertain to selective photo-enhanced wet oxidation for nitride layer regrowth on substrates. In one aspect, a semiconductor structure may comprise: a first substrate structure; a III-nitride structure bonded with the first substrate structure; a plurality of air gaps formed between the first substrate structure and the III-nitride structure; and a III-oxide layer formed on surfaces around the air gaps, wherein a portion of the III-nitride structure including surfaces around the air gaps is transformed into the III-oxide layer by a selective photo-enhanced wet oxidation, and the III-oxide layer is formed between an untransformed portion of the III-nitride structure and the first substrate structure.

Abstract: A light emitting diode comprises a permanent substrate having a chip holding space formed on a first surface of the permanent substrate; an insulating layer and a metal layer sequentially formed on the first surface of the permanent substrate and the chip holding space, wherein the metal layer comprises a first area and a second area not being contacted to each other; a chip having a first surface attached on a bottom of the chip holding space, contacted to the first area of the metal layer; a filler structure filled between the chip holding space and the chip; and a first electrode formed on a second surface of the chip. The chip comprises a light-emitting region and an electrical connection between the first area of the metal layer and the light emitting region is realized by using a chip-bonding technology.