Abstract: Embodiments of a system are described. This system includes an array of chip modules (CMs) and a baseplate, where the baseplate is configured to communicate data signals via optical communication. Moreover, the array includes first CMs mechanically coupled to first alignment features on the baseplate, and adjacent second CMs mechanically coupled to second alignment features on the baseplate. In this array, a given first CM is electrically coupled to a given set of electrical proximity connectors. Additionally, the array includes bridge components, wherein a given bridge component is electrically coupled to the second SCM and another set of electrical proximity connectors, which is electrically coupled to the set of electrical proximity connectors, thereby facilitating communication of other data signals between adjacent first CMs and second CMs via electrical proximity communication.

Abstract: A system and method for management of resource allocation for speculative fetched instructions following small backward branch instructions. An instruction fetch unit speculatively prefetches a memory line for each fetched memory line. Each memory line may have a small backward branch instruction, which is a backward branch instruction that has a target instruction within the same memory line. For each fetched memory line, the instruction fetch unit determines if a small backward branch instruction exists among the instructions within the memory line. If a small backward branch instruction is found and predicted taken, then the instruction fetch unit inhibits the speculative prefetch for that particular thread. The speculative prefetch may resume for that thread after the branch loop is completed. System resources may be better allocated during the iterations of the small backward branch loop.

Abstract: In general, the invention relates to a method for migrating virtual machines. The method includes obtaining migration criteria for a first virtual machine (VM) where the migration criteria is a bandwidth constraint for the first VM. The method further includes sending a request comprising the migration criteria to a second computer in the chassis, receiving a response to request from the second computer, where response indicates that the second computer can satisfy the migration criteria. The method further includes suspending execution of the first VM on the first computer and obtaining information to migrate the first VM, migrating the first VM and a first VNIC associated with the first VM, updating a virtual switching table in the chassis to reflect the migration of the first VM; and resuming execution of the first VM on the second computer.

Abstract: There is provided an information processing apparatus. The apparatus comprises: a processor; at least one I2C device; and a processor support chip. The processor support chip comprises a local service controller and a jointly addressable memory space and has an interface to the processor for the transfer of information therebetween. The processor support chip also has an interface for communication with a service processor; and an I2C interface for communication with the at least one I2C device. The local service controller has exclusive read and write access to the I2C interface; and is operable to maintain a data structure indicating a current value associated with the I2C device in the jointly addressable memory space for access by the processor and the service processor.

Abstract: According to a technique described herein, a binding document comprises one or more “<bind>” element instances. Each “<bind>” element instance indicates an association between (a) an SVG element instance and (b) a class. When a binding's name is passed to a “createFromTemplate( )” method, the method processes all of the “<bind>” element instances that are associated within that name. For each such “<bind>” element instance, the method (a) creates, in an SVG DOM tree, a clone of a node that corresponds to an SVG element instance indicated in that “<bind>” element instance, (b) instantiates an object that is an instance of a class that is indicated in that “<bind>” element instance, and (c) stores data that establishes a binding between the clone node and the object. Methods of the object can be invoked to affect and/or alter attributes of the clone node to which the object is bound.

Abstract: In one embodiment, the branch prediction mechanism includes a first storage including a first plurality of locations for storing a first set of partial prediction information. The branch prediction mechanism also includes a second storage including a second plurality of locations for storing a second set of partial prediction information. Further, the branch prediction mechanism includes a control unit that performs a first hash function on input branch information to generate a first index for accessing a selected location within the first storage. The control unit also performs a second hash function on the input branch information to generate a second index for accessing a selected location within the second storage. Lastly, the control unit further provides a prediction value based on corresponding partial prediction information in the selected locations of the first and the second storages.

Abstract: A method for compensating negative bias temperature instability (NBTI) effects on a given model of transistors includes monitoring the NBTI effects on the transistors over time, determining a change in a threshold voltage of the transistors over time based on the monitoring, determining a forward bias voltage based on the change in threshold voltage, and applying the forward bias voltage to the transistors over time. The method may further include storing the monitoring results in a lookup table, and adjusting the forward bias voltage based on the lookup table. The monitoring may include emulating the NBTI effects on a system comprising a plurality of semiconductor devices in which the transistors are used.

Abstract: A receiver circuit uses two or more comparators to detect the received data signal. Each comparator is set to compare the data signal to a different reference signal. The output signals of the comparators are received into a detector circuit, which provides a third output signal that establishes the logic state of the received signal based on whether or not the output signals of the comparators are equal. Depending on the logic state of the data signal, one of the comparators provides its output signal sooner than the other. Each comparator may be implemented by a differential amplifier. In one embodiment, the reference signals are threshold voltages which may be provided by the tripping voltages at the trip points for the logic HIGH and LOW states.

Abstract: A Nyquist sampling frequency is determined for performance counter events to be measured. Based on the Nyquist sampling frequencies, a schedule for measuring the performance counter events is determined. The performance counter event measurements are then conducted in accordance with the schedule, whereby the measurements yield a set of sample data for each performance counter event. A signal reconstruction algorithm is applied to the set of sample data for each performance counter event to reconstruct an essentially complete signal for each performance counter event. The essentially complete signal for each performance counter event is then used to improve either a design or a utilization of either a microprocessor or an application to be executed on the microprocessor.

Abstract: Small and power-efficient buffer/mini-cache sources and sinks selected DMA accesses directed to a memory space included in a coherency domain of a microprocessor when cached data in the microprocessor is inaccessible due to any or all of the microprocessor being in a low-power state not supporting snooping. Satisfying the selected DMA accesses via the buffer/mini-cache enables reduced power consumption by allowing the microprocessor (or portion thereof) to remain in the low-power state. The buffer/mini-cache may be operated (temporarily) incoherently with respect to the cached data in the microprocessor and flushed before deactivation to synchronize with the cached data when the microprocessor (or portion thereof) transitions to a high-power state that enables snooping. Alternatively the buffer/mini-cache may be operated in a manner (incrementally) coherent with the cached data.

Abstract: Various methods and apparatus for executing a multithreaded algorithm that performs a static timing analysis of an integrated circuit chip (chip) include logic for traversing the chip to identify a plurality of components (cells or nodes) within a chip circuit of the chip. A waveform graph is defined for the identified nodes. One or more virtual graphs are generated from the waveform graph. The plurality of nodes in the one or more virtual graphs are processed using multiple threads to obtain quadruplet of time domain dataset values representing the different modes of propagation for each node. A timing check is performed at an end node of the virtual graphs using the quadruplet of time domain dataset values to determine any timing violation within the chip design.

Abstract: A method for indentifying instances of a smaller circuit in a larger circuit is disclosed. Both the smaller circuit and the larger circuit have a plurality of vertices. A vertex is one of a device or a net. The device, such a transistor, includes a Gate, a Drain, and a Source. The net is a wired connection between devices. In this method, one initial unique label is assigned to each of the plurality of vertices, each of a plurality of connection-types, power connection, and ground connection. A zero label is assigned to each of an input/output ports and a same initial unique label is assigned to same types of circuit components. Then each net is relabeled using labels of neighboring vertices. The neighboring vertices of a vertex are vertices that are directly connected to the vertex. Then, each device in the plurality of vertices is relabeled using labels of neighboring vertices excluding a label of a vertex that is connected to the Gate of the each device.

Abstract: A system and method of deterministically transferring data from a first clock domain to a second clock domain includes writing data to a buffer, communicating a read status from the first clock domain to the second clock domain and reading data from the buffer into the second clock domain at a clock rate of the second domain. The buffer is accessible by both one or more devices in each of the first clock domain and the second clock domain and the read status is communicated from the first clock domain to the second clock domain when the second clock domain enables the read status to be communicated from the first clock domain to the second clock domain.

Abstract: Disclosed are improved methods, devices and systems for storage management in digital networks.

Abstract: A mechanism is provided for estimating the computing resources needed to execute a job. The mechanism receives a request to execute a new job. The mechanism processes the request to determine a set of job characteristics for the new job, and accesses a database containing execution information for a plurality of previously executed jobs. The mechanism obtains from the database a set of execution information associated with a particular previously executed job having similar or identical job characteristics as the new job. From this execution information, the mechanism determines what computing resources were actually used to execute the particular previously executed job. Then, based upon this information, the mechanism derives an estimate of the computing resources needed to execute the new job. By estimating the needed resources in this manner, the mechanism relieves the user of having to guess at what resources will be needed to execute a job.

Abstract: An instruction processing circuit includes an instruction cache, a decoder configured to receive at least one of the instructions and to generate, based thereon, a decoder sequence of at least one operation. The circuit includes a basic block cache that includes a basic block sequence of at least one of the operations. The basic block sequence is derived from at least one of the decoder sequences and includes at most one conditional control transfer operation. The circuit includes a multi-block cache that includes a multi-block sequence consisting of at least one of the operations derived from two or more smaller op sequences. A sequencer is configured to generate a prediction for the result of a conditional control transfer operation, select the next sequence of operations, and provide an indication of the next sequence to the instructions cache, the basic block cache, and the multi-block cache.

Abstract: A memory device having a split power switch is provided to improve the writeability of static random access memory (SRAM) cells without adversely compromising their stability. For example, various split power switch circuits are used to permit the voltage or current of a power supply line connected with one side of an SRAM cell to drop during write operations. This drop weakens one side of the SRAM cell and reduces the drive-fight between transistors of the SRAM cell and external write circuitry. As a result, the minimum voltage for writing new logic states into the SRAM cell is reduced to permit overall lower operating voltages for the SRAM cell and related circuitry. By continuing to maintain a second side of the SRAM cell at the reference voltage or current, the SRAM cell can successfully switch to a newly written logic state.

Abstract: An instruction processing circuit for a processor includes a decoder circuit, a cache circuit, a sequencer circuit operable to select a next sequence of operations, and an operations fetch circuit operable to convey the next sequence of operations to an execution circuit, receive an indication that a sequencing action of the sequencer circuit is sequencing ahead of the execution circuit, and switch, based on the indication, a source of the operations fetch circuit between the cache circuit and the decoder circuit.

Abstract: A system and method of analyzing a power grid in an integrated circuit includes inputting a circuit design to a test bench, inputting a plurality of initial values for the circuit design in to the test bench, setting a current time t to 0 value for an initial time (t0) of the operation of the circuit design, representing each capacitor in an RC circuit corresponding to the power grid circuit design by the each capacitor's respective time variant equivalent companion model, describing each one of the plurality of RC equivalent circuits mathematically as one of a corresponding plurality of linear equations, storing the plurality of linear equations in a matrix Y0 for time t0, resolving the matrix Y0 to determine a DC operating point, updating the RC equivalent circuits and the corresponding plurality of linear equations at a second time step t1=t+h where h is a time step value equal to the current time t and a next simulated operation time, storing the updated plurality of linear equations in a matrix Y1 for ti

Abstract: Method and apparatus for tagged references for identifying thread-local data in multithreaded applications. Embodiments may provide a dynamic mechanism that identifies thread-local objects by “tagging” references to the objects. In embodiments, in an application, if an object is to be allocated as a thread-local object, one or more bits of the object reference may be “tagged” to indicate that the object is a thread-local object. In one embodiment, the lowest-order bit of the object reference may be set to indicate that the object is a thread-local object. In embodiments, thread locality of an object may be determined by testing the reference itself rather than loading a bit or field from the referenced object or by checking address ranges. Further, embodiments do not rely on address ranges to identify objects as thread-local, and so the allocation of thread-local objects may not be restricted to thread-local heaps.