Abstract: Optimized dose assignments are determined for each portion of a layout by utilizing an improved proximity function and additional dose correction functions in performing a short range proximity effect correction. The optimized dose assignments are determined to minimize critical dimension (CD) deviations and maintain CD linearity across different feature sizes. The improved proximity function and additional dose correction functions are determined by calibration based on experimental CD measurements of test designs. The improved proximity function includes a sum of more than two Gaussian functions, each having an associated effect range and an associated weight, wherein one or more of the associated weights may be negative. The additional dose correction functions include an iso-dense bias correction function and a dose evaluation point displacement function for line end shortening correction.

Abstract: A test structure for localizing shorts in an integrated circuit and method of testing is described. A first comb structure is formed from a first busbar and a first plurality of fingers extending from the first busbar. A second comb structure formed from a second busbar and a second plurality of fingers extending from the second busbar. The second plurality of fingers is interleaved with the first plurality of fingers. A plurality of pass gates is connected between the first plurality of fingers and the first busbar. A pass gate terminal is electrically connected to the gate electrode of each of the plurality of pass gates. When the pass gates are turned OFF thereby disconnecting the first busbar from the first plurality of fingers, voltage contrast imaging can be used to identify which of the first fingers is adjacent the short.

Abstract: A method comprises the steps of: (a) simulating on a processor a fabrication of a plurality of layout patterns by a lithographic process; (b) determining sensitivities of the layout patterns to a plurality of parameters based on the simulation; (c) using the sensitivities to calculate deviations of the patterns across a range of each respective one of the parameters; and (d) selecting ones of the patterns having maximum or near-maximum deviations to be used as test patterns.

Abstract: A layout for devices under test formed on a semiconductor wafer for use in wafer testing includes a first array of devices under test and a first pad set formed adjacent to the first array. The first pad set includes a gate force pad, a source pad, and a drain pad. Each of the devices under test in the first array is connected to the gate pad of the first pad set. Each of the devices under test in the first array is connected to the source pad of the first pad set. Each of the devices under test in the first array is connected to the drain pad of the first pad set.

Abstract: Fast localization of electrically measured defects of integrated circuits includes providing information for fabricating a test chip having test structures configured for parallel electrical testing. The test structures on the test chip are electrically tested employing a parallel electrical tester. The results of the electrical testing are analyzed to localize defects on the test chip.

Abstract: A method for evaluating the quality of data collection in a manufacturing environment is provided. Said data are intended to be analyzed by a process control system. The method comprising the following steps (A) collecting raw data according to a Data Collection plan specifying, and for each data item, a sampling time reference indicating at which time interval it is expected, and associating to each collected data item a timestamp indicating its actual collection time, (B) for at least a part of the raw data included inside a predetermined window, determining a Data Collection Quality Value (DCQV) by: (a) reading the timestamps; (b) computing at least one quality indicator value from the relationship between each timestamp and the corresponding time reference, wherein a shift represents a malfunction of the equipment or of the data collection system; (c) after steps (b) and (c) have been performed for all data items, computing a single data collection quality value (DCQV) indicator for said time window.

Abstract: A die placement of dice to be formed on a semiconductor wafer is adjusted by obtaining a die placement and one or more locations on the wafer contacted by one or more processing structures or a substance emitted by one or more processing structures. The die placement is adjusted based on the obtained one or more locations on the wafer.

Abstract: In one embodiment, wafers are processed to build test structures in the wafers. The wafers may be processed in tools of process steps belonging to a process module. The test structures may be tested to obtain defectivity data. Tool process parameters may be monitored and collected as process tool data. Other information about the wafers, such as metrology data and product layout attribute, may also be collected. A model describing the relationship between the defectivity data and process tool data may be created and thereafter used to relate the process tool data to a yield of the process module. The model may initially be an initial model using process tool data from a limited number of test wafers that contain test structures. The model may also be an expanded model using process tool data from product wafers containing embedded test structures in areas with no product devices.

Abstract: A layout for devices under test formed on a semiconductor wafer for use in wafer testing includes a first array of devices under test and a first pad set formed adjacent to the first array. The first pad set includes a gate force pad, a source pad, and a drain pad. Each of the devices under test in the first array is connected to the gate pad of the first pad set. Each of the devices under test in the first array is connected to the source pad of the first pad set. Each of the devices under test in the first array is connected to the drain pad of the first pad set.

Abstract: Systems and methods for electrical characterization of inter-layer alignment. In one embodiment, a wafer including a plurality of test structures are accessed. The plurality of test structures include chains of conductive segments on multiple layers, coupled by vias. The plurality of test structures are designed with varying amounts of intentional misalignment between the multiple layers. The reactance of each of the plurality of test structures is measured. The reactance is analyzed to determine the process-induced inter-layer misalignment of the integrated circuit wafer.

Abstract: An integrated circuit is designed to improve yield when manufacturing the integrated circuit, by obtaining a design element from a set of design elements used in designing integrated circuits. A variant design element is created based on the obtained design element, where a feature of the obtained design element is modified to create the variant design element. A yield to area ratio for the variant design element is determined. If the yield to area ratio of the variant design element is greater than a yield to area ratio of the obtained design element, the variant design element is retained to be used in designing the integrated circuit.

Abstract: A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process.

Abstract: In one exemplary embodiment, yield information of semiconductor dice is mapped by obtaining yield information of a first die that was formed on a first location on a first wafer. Yield information is obtained of a second die that was formed on a second location on a second wafer. A portion of the first location corresponds to a portion of the second location such that the portion of the first location would overlap with the portion of the second location if the first location was on the second wafer. A plurality of pixel elements is defined. Each pixel element corresponds to a different location on a wafer, and at least one of the plurality of pixel elements corresponds to the portion of the first location that corresponds to the portion of the second location. An average yield is determined for the at least one of the plurality of pixel elements based on the yield information of the first die and the second die.

Abstract: A hot spot is identified within a mask layout design. The hot spot represents a local region of the mask layout design having one or more feature geometries susceptible to producing one or more fabrication deficiencies. A test structure is generated for the identified hot spot. The test structure is defined to emulate the one or more feature geometries susceptible to producing the one or more fabrication deficiencies. The test structure is fabricated on a test wafer using specified fabrication processes. The as-fabricated test structure is examined to identify one or more adjustments to either the feature geometries of the hot spot of the mask layout design or the specified fabrication processes, wherein the identified adjustments are capable of reducing the fabrication deficiencies.

Abstract: A method for analyzing a sample of wafers includes identifying F failure metrics applicable to at least one pattern on each wafer within the sample. Z spatial and/or reticle zones are identified on each wafer, where Z and F are integers. Values are provided for each failure metric, for each zone on each wafer. A point is defined for each respective wafer in an N-dimensional space, where N=F*Z, and each point has coordinates corresponding to values of the F failure metrics in each of the zones of the corresponding wafer. The sample of wafers is partitioned into a plurality of clusters, so that the wafers within each clusters are close to each other in the N-dimensional space. A plurality of clusters is thus identified from the sample of wafers so that within each individual cluster, the wafers have similar defects to each other.

Abstract: A test cell for localizing defects includes a first active region, a second active region formed substantially parallel to the first active region, a third active region formed substantially parallel to the first and second active regions, a fourth active region formed between the first and second active regions, and a fifth active region formed between the second and third active regions. The fourth and fifth active regions are formed adjacent to opposite end portions of the second active region. The fourth and fifth active regions are also formed substantially perpendicular to the second active region.

Abstract: A test vehicle comprises at least one product layer having a east one product circuit pattern on the product layer, and one or more clone layers formed over the product layer (1902). The one or more clone layers include a plurality of structures, which may include clone test vehicle circuit patterns and/or clone test vehicle vias (1902). The presence of one or more defects (1904) in the one or more clone layers (1908) is an indicator of a tendency of the product circuit pattern to impact yield of a succeeding layer to be formed over the product circuit pattern in a product (1910).

Abstract: A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process.

Abstract: A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process.

Abstract: A test structure comprising a test pattern is formed on a substrate. The test pattern includes a first comb structure having a plurality of tines, and a second structure. The second structure may be a snake structure having a plurality of side walls or a second comb structure having a plurality of side walls. The tines of the first comb structure are positioned within side walls of the snake structure or second comb structure. The tines of the first comb structure are offset from a center of the side walls. Test data collected from the test structure are analyzed, to estimate product yield. The test structure may have a lower layer pattern, such that topographical variations of the lower layer pattern propagate to an upper layer pattern of the test structure.