Abstract: A method is disclosed for localizing product yield variability to a process module. The method includes obtaining fail rate and critical area data for each process module layer in a number of test chips. A variance in a defect density (DD) probability density function (PDF) is determined based on the obtained fail rate and critical area data for each process module layer. A percent contribution from each process module layer to the variance in DD PDF is determined. Based on the determined percent contribution to the variance in DD PDF from each process module layer, one or more process module layers are identified as contributing to the determined variance in the DD PDF. Additionally, a method is provided to assess the impact on product yield due to reduction in the yield variability associated with a particular process module layer.

Abstract: A Characterization Vehicle (CV) and a method for forming it which yields a gain in efficiency for IC yield ramp improvements by enabling faster learning cycles and diagnosis while reducing costs. A plurality of SF experiments are combined into a single full flow mask set with many inline testing points. Smaller pads are arranged in a way supporting testing of interleaved pad frames, parallel testing, and the usage of stacked test structures, or Devices Under Test (DUT's).

Abstract: A test chip comprises at least one level having an array of regions. Each region is capable of including at least one test structure. At least some of the regions include respective test structures. The level has a plurality of driver lines that provide input signals to the test structures. The level has a plurality of receiver lines that receive output signals from the test structures. The level has a plurality of devices for controlling current flow. Each test structure is connected to at least one of the driver lines with a first one of the devices in between. Each test structure is connected to at least one of the receiver lines with a second one of the devices in between, so that each of the test structures can be individually addressed for testing using the driver lines and receiver lines.

Abstract: A method and system is described for mapping a system-level description of an integrated system directly to a technology-specific set of logic cells that are comprised primarily of large complex cells (bricks). The invention is based on applying aggressive Boolean operations that would be of impractical runtime complexity for a large library, but are applicable for the targeted brick libraries which typically contain a small number of complex cells, along with a much smaller number of simple cells. This invention is modular such that it can be applied in the context of incremental netlist optimization as well as optimization during physical synthesis.

Abstract: A method for predicting an impact on post-repair yield resulting from manufacturing process modification is described. The method includes receiving bit data representing locations of defective memory cells for a plurality of memory devices. The bit data is modified by removing a selected failure pattern type according to a modification scheme to generate modified bit data. Repairs are simulated on hypothetical memory devices corresponding to the modified bit data, generating a result indicating whether the hypothetical memory device is good or bad. A post-repair yield is then identified and a report is generated indicating the post-repair yield, the post-repair yield representing a number of the plurality of memory devices that would be functional after repair had the plurality of memory devices been manufactured without the selected failure pattern. A method to identify a process providing the best economic benefit is also described.

Abstract: The invention provides a reduced complexity layout style based on applying a limited set of changes to an underlying repeated base template. With the templates properly defined in accordance with the characteristic features disclosed, the invention enables efficient implementation of logic circuitry, with a dramatic reduction in the pattern complexity (or number of unique layout patterns at each mask level) for realistically sized designs. This reduction in pattern complexity that the invention provides is particularly important for advanced and emerging semiconductor processes, because it enables effective use of SMO and full-chip mask optimization.

Abstract: The invention provides a reduced complexity layout style based on applying a limited set of changes to an underlying repeated base template. With the templates properly defined in accordance with the characteristic features disclosed, the invention enables efficient implementation of logic circuitry, with a dramatic reduction in the pattern complexity (or number of unique layout patterns at each mask level) for realistically sized designs. This reduction in pattern complexity that the invention provides is particularly important for advanced and emerging semiconductor processes, because it enables effective use of SMO and full-chip mask optimization.

Abstract: A test vehicle and method for electrical characterization of misalignment, for example resulting from double patterning processes, that enables characterization of patterns on wafers which have finished processing. It includes a structure and method for measurement of a space-sensitive electrical parameter to characterize gaps between features of different sub-patterns on a semiconductor wafer portion, and may further comprise a test structure for measuring feature dimensions.

Abstract: Systems and methods for detecting and monitoring Nickel-silicide process and induced failures. In a first method embodiment, a method of characterizing a Nickel-silicide semiconductor manufacturing process includes accessing a test chip including a parallel coupled chain of transistors, wherein the transistors are designed for inducing stress into Nickel-silicide features of the transistors, and for increasing a probability of a manufacturing failure of the Nickel-silicide features. A biasing voltage is applied to one terminal of the parallel coupled chain, all other terminals of the parallel coupled chain and grounded, and current is measured at each of the all other terminals of the parallel coupled chain. This process is repeated for each terminal of the parallel coupled chain. The measured currents from all possible conduction paths are compared to determine a manufacturing defect in the parallel coupled chain of transistors.

Abstract: The invention provides a method and process for designing an integrated circuit based on using the results from both 1) a specific set of silicon test structure characterizations and 2) the decomposition of logic into combinations of simple logic primitives, from which a set of logic bricks are derived that can be assembled for a manufacturable-by-construction design. This implementation of logic is compatible with the lithography settings that are used for implementation of the memory blocks and other components on the integrated circuit, particularly by implementing geometrically consistent component features. The invention provides the ability to recompile a design comprised of logic and memory blocks onto a new geometry fabric to implement a set of technology-specific design changes, without requiring a complete redesign of the entire integrated circuit.

Abstract: Circuits for performing four terminal measurement point (TMP) testing of devices under test (DUT) is provided. The DUT and the circuit is to be defined on a semiconductor chip. The circuit includes a DUT having a first terminal and a second terminal, where the first terminal of the DUT is connectable to a first terminal measurement point and a third terminal measurement point, and the second terminal of the DUT is connectable to a second terminal measurement point and a fourth terminal measurement point. A first transistor is provided to select access to the first terminal measurement point, a second transistor is provided to select access to the third terminal measurement point, a third transistor is provided to select access to the second terminal measurement point; and a fourth transistor is provided to select access to the fourth terminal measurement point.

Abstract: A global predictive monitoring system for a manufacturing facility. The system may be employed in an integrated circuit (IC) device fabrication facility to monitor processing of semiconductor wafers. The system may include deployment of a swarm of individually separate agents running in computers in the facility. Each agent may comprise a genetic algorithm and use several neural networks for computation. Each agent may be configured to receive a limited set of inputs, such as defectivity data and WIP information, and calculate a risk from the inputs. A risk may be a value indicative of a production yield. Each agent may also generate a quality value indicative of a reliability of the risk value. New agents may be generated from the initial population of agents. Outputs from the agents may be collected and used to calculate projections indicative of a trend of the production yield.

Abstract: A test structure for localizing shorts in an integrated circuit and method of testing is described. A first comb structure is formed from a first busbar and a first plurality of fingers extending from the first busbar. A second comb structure formed from a second busbar and a second plurality of fingers extending from the second busbar. The second plurality of fingers is interleaved with the first plurality of fingers. A plurality of pass gates is connected between the first plurality of fingers and the first busbar. A pass gate terminal is electrically connected to the gate electrode of each of the plurality of pass gates. When the pass gates are turned OFF thereby disconnecting the first busbar from the first plurality of fingers, voltage contrast imaging can be used to identify which of the first fingers is adjacent the short.

Abstract: A method and system are described to group logic terms at a higher level of abstraction than that found using standard cells to implement the logic functions using a reduced number of transistors, and to reduce the total number of unique geometry patterns needed to create the integrated circuit implementation. By grouping the logic functions in terms of a larger number of literals (logic variable inputs), the functions can be implemented in terms of a number of transistors that is often less and no more than equal to that which is required for implementing the same function with a number of logic primitives, or simpler standard logic cells. The optimized transistor level designs are further optimized and physically constructed to reduce the total number of unique geometry patterns required to implement the integrated circuit.

Abstract: A test cell for localizing defects includes a first active region, a second active region formed substantially parallel to the first active region, a third active region formed substantially parallel to the first and second active regions, a fourth active region formed between the first and second active regions, and a fifth active region formed between the second and third active regions. The fourth and fifth active regions are formed adjacent to opposite end portions of the second active region. The fourth and fifth active regions are also formed substantially perpendicular to the second active region.

Abstract: A method and system is described for mapping a system-level description of an integrated system directly to a technology-specific set of logic cells that are comprised primarily of large complex cells (bricks). The invention is based on applying aggressive Boolean operations that would be of impractical runtime complexity for a large library, but are applicable for the targeted brick libraries which typically contain a small number of complex cells, along with a much smaller number of simple cells. This invention is modular such that it can be applied in the context of incremental netlist optimization as well as optimization during physical synthesis.

Abstract: Methods for determining customized defect detection inspection plans are provided. One method includes fabricating a test chip and generating test chip data from the fabricated test chip. Then, defining systematic signatures from the generated test chip data and identifying a yield relevant systematic signature from the defined systematic signatures. The method includes identifying a layout pattern associated with the yield relevant systematic signature and locating the identified layout pattern on a process module layer of a product chip. Further, the method includes defining a customized defect detection inspection or metrology methodology for detecting systematic defects on the process module layer based on the identified layout pattern associated with the yield relevant systematic signature.

Abstract: A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process.

Abstract: A printability simulation is performed on a mask layout over a range of lithography process conditions. A layout configuration capable of inducing functional or parametric failure in a semiconductor device is identified in the mask layout. A test structure representative of the identified layout configuration is obtained. A design of experiment is associated with the test structure. The design of experiment is defined to investigating effects of variations of one or more layout attributes in the test structure. Multiple instance of the test structure are fabricated on a wafer according to the design of experiment. Electrical performance characteristics of the fabricated test structures are measured. Based on the measured electrical performance characteristics, one or more layout attributes of the test structure capable of causing functional or parametric failure are determined.

Abstract: Optimized dose assignments are determined for each portion of a layout by utilizing an improved proximity function and additional dose correction functions in performing a short range proximity effect correction. The optimized dose assignments are determined to minimize critical dimension (CD) deviations and maintain CD linearity across different feature sizes. The improved proximity function and additional dose correction functions are determined by calibration based on experimental CD measurements of test designs. The improved proximity function includes a sum of more than two Gaussian functions, each having an associated effect range and an associated weight, wherein one or more of the associated weights may be negative. The additional dose correction functions include an iso-dense bias correction function and a dose evaluation point displacement function for line end shortening correction.