Abstract: A method of optimizing production of semiconductor devices on a wafer comprises steps of characterizing at least one effect of at least one manufacturing component on at least one optimization criterion; inputting user optimization data; and, based on the at least one effect and the user optimization data, performing optimization to determine a layout of semiconductor devices on the wafer that optimizes performance according to the user optimization data.

Abstract: A method for improving yield of a process for fabricating a read-only memory (ROM) includes evaluating a yield of a ROM fabrication process associated with a first ROM design. At least two candidate ROM design modifications are identified. At least one of the candidate ROM design modifications comprises inversion of bit values of data to be stored in the ROM. A plurality of criteria are applied, including at least an amount of yield improvement and a difficulty of implementation associated with each candidate ROM design modification. One of the candidate ROM design modifications is selected based on the application of the criteria. A modified ROM fabrication process is performed to fabricate a ROM according to the selected ROM design modification.

Abstract: For methods of creating pluralities of semiconductor test structure layouts from a graphical specification, systems include a GUI to draw objects representing shapes of such layout, and to parameterize those objects to size and interrelate those objects. The GUI supports placement of cells in hierarchical layers. The graphical specification is parsed into an ASCII descriptor file from which node information is extracted and connection information among nodes preserved in separate graphs for an X direction and a Y direction of the layout. That node and connection information is further processed to obtain equations having variables (parameters) that relate points in the layout a defined point, and those equations used in forming source code that can be executed with values for the variables in the source code.

Abstract: A method for evaluating the quality of data collection in a manufacturing environment is provided. Said data are intended to be analyzed by a process control system. The method comprising the following steps (A) collecting raw data according to a Data Collection plan specifying, and for each data item, a sampling time reference indicating at which time interval it is expected, and associating to each collected data item a timestamp indicating its actual collection time, (B) for at least a part of the raw data included inside a predetermined window, determining a Data Collection Quality Value (DCQV) by: (a) reading the timestamps; (b) computing at least one quality indicator value from the relationship between each timestamp and the corresponding time reference, wherein a shift represents a malfunction of the equipment or of the data collection system; (c) after steps (b) and (c) have been performed for all data items, computing a single data collection quality value (DCQV) indicator for said time window.

Abstract: The invention provides a method and process for designing an integrated circuit based on using the results from both 1) a specific set of silicon test structure characterizations and 2) the decomposition of logic into combinations of simple logic primitives, from which a set of logic bricks are derived that can be assembled for a manufacturable-by-construction design. This implementation of logic is compatible with the lithography settings that are used for implementation of the memory blocks and other components on the integrated circuit, particularly by implementing geometrically consistent component features. The invention provides the ability to recompile a design comprised of logic and memory blocks onto a new geometry fabric to implement a set of technology-specific design changes, without requiring a complete redesign of the entire integrated circuit.

Abstract: A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process.

Abstract: Dice on a wafer are selected to be tested using a yield map. The yield map incorporates yield information of different products produced by the same fabrication process. A die placement for a product to be produced by the same process is determined based on the yield map. An expected yield for a die in the die placement is also determined based on the yield map. The expected yield for the die is then used to determine whether to test the die.

Abstract: A die placement of dice to be formed on a semiconductor wafer is adjusted by obtaining a die placement and one or more locations on the wafer contacted by one or more processing structures or a substance emitted by one or more processing structures. The die placement is adjusted based on the obtained one or more locations on the wafer.

Abstract: A layout for devices under test formed on a semiconductor wafer for use in wafer testing includes a first array of devices under test and a first pad set formed adjacent to the first array. The first pad set includes a gate force pad, a source pad, and a drain pad. Each of the devices under test in the first array is connected to the gate pad of the first pad set. Each of the devices under test in the first array is connected to the source pad of the first pad set. Each of the devices under test in the first array is connected to the drain pad of the first pad set.

Abstract: A test structure combines a first structure (1010) for erosion evaluation with a second structure (1000) for extraction of defect size distributions. The first structure (1010) is a loop structure usable determine a resistance value that varies with metal height. The second structure is a NEST structure (1000). Loop lines of the loop structure (1010) are connected on both sides of the NEST structure (1000).

Abstract: A die placement of dies on a wafer is selected to reduce test time of the dies by obtaining a die placement and determining placements of a tester head needed to test the dies in the die placement. A number of touchdowns needed in the determined placements of the tester head is determined, where a touchdown involves lowering the tester head to form an electrical contact between pins on the tester head and bonding pads on a die being tested. The die placement is adjusted to reduce the number of touchdowns.

Abstract: A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process.

Abstract: A die placement of dice to be formed on a semiconductor wafer is adjusted by obtaining a die placement and one or more locations on the wafer contacted by one or more processing structures or a substance emitted by one or more processing structures. The die placement is adjusted based on the obtained one or more locations on the wafer.

Abstract: A test vehicle (100) comprises a substrate (99), a plurality of nested serpentine lines (202) on the substrate, and a plurality of test pads (204) on the substrate. Each serpentine line has a plurality of turn sections that comprise two parallel line segments connected by a perpendicular line segment. Each of the plurality of test pads is connected to a respective turn section of a respective one of the nested serpentine lines. Each pair of test pads connected to one of the subset of the nested serpentine lines has at least a respectively different turn section portion connected therebetween.

Abstract: A semiconductor wafer having a plurality of dice formed on the wafer. The plurality of dice having non-rectangular shapes with at least one notched corner. A plurality of saw streets are defined between the plurality of dice. At an intersection of two of the plurality of saw streets, a distance is defined between corners of two adjacent dice that is greater than a minimum distance between the two adjacent dice.

Abstract: A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process.

Abstract: A structure and method passivates dangling silicon bonds by the introduction of deuterium into a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) by ion implantation. The process of implantation provides precise placement of deuterium at optimum locations within the gate stack to create stable silicon-deuterium bond terminations at the Si—SiO2 interface within the gate-channel region. The deuterium is encapsulated in the MOSFET by the use of a Silicon Nitride (SiN) barrier mask. The ability of deuterium to passivate dangling silicon bonds is maximized by removing hydrogen present in the MOSFET and by use of an absorption layer to create a deuterium rich region.

Abstract: A method for selecting a process for forming a device, includes generating a plurality of equations using a response surface methodology model. Each equation relates a respective device simulator input parameter to a respective combination of processing parameters that can be used to form the device or a respective combination of device characteristics. A model of a figure-of-merit circuit is formed that is representative of an integrated circuit into which the device is to be incorporated. One of the combinations of processing parameters or combinations of device characteristics is identified that results in a device satisfying a set of performance specifications for the figure-of-merit circuit, using the plurality of equations and the device simulator.

Abstract: An integrated circuit is designed to improve yield when manufacturing the integrated circuit, by obtaining a design element from a set of design elements used in designing integrated circuits. A variant design element is created based on the obtained design element, where a feature of the obtained design element is modified to create the variant design element. A yield to area ratio for the variant design element is determined.

Abstract: Publishable yield information can be produced by obtaining an actual yield value associated with an integrated circuit (IC) or portion of an IC formed on each one of a plurality of wafers using a semiconductor wafer fabrication process. An average yield value associated with a plurality of ICs or portions of an IC formed on each one of the plurality of wafers using the semiconductor fabrication process is determined. A transformed yield value associated with the IC or portion of an IC is generated using the actual yield value and the average yield value.