Patents Assigned to Peregrine Semiconductor Corporation
  • Patent number: 9948281
    Abstract: Methods and devices providing Positive Logic biasing schemes for use in a digitally tuning capacitor in an integrated circuit device are described. The described methods can be used in integrated circuits with stringent requirements in terms of switching time, power handling, noise sensitivity and power consumption. The described devices include DC blocking capacitors arranged in series with stacked switches coupled to RF nodes. The stacked FET switches receive non-negative supply voltages through their drains and gates during the ON and OFF states to adjust the capacitance between the two nodes.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: April 17, 2018
    Assignee: Peregrine Semiconductor Corporation
    Inventor: Tero Tapio Ranta
  • Patent number: 9912327
    Abstract: Systems, methods, and apparatus for use in biasing and driving high voltage semiconductor devices using only low voltage transistors are described. The apparatus and method are adapted to control multiple high voltage semiconductor devices to enable high voltage power control, such as power amplifiers, power management and conversion and other applications wherein a first voltage is large compared to the maximum voltage handling of the low voltage control transistors. Timing of control signals can be adjusted via internal and/or external components so as to minimize shoot trough currents in the high voltage devices. A DC/DC power conversion implementation from high input voltage to low output voltage using a novel level shifter which uses only low voltage transistors is also provided. Also presented is a level shifter in which floating nodes and high voltage capacitive coupling and control enable the high voltage control with low voltage transistors.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: March 6, 2018
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Buddhika Abesingha, Merlin Green
  • Patent number: 9906208
    Abstract: An electronic system that includes a digitally selectable phase shifter circuit and an insertion loss fine adjustment circuit such that the system as a whole exhibits little or no change in insertion loss when changing phase state, and/or a digitally selectable attenuator circuit and a phase fine adjustment circuit such that the system as a whole exhibits little or no effect on phase when changing attenuation state. Included are methods for selecting adjustment control words for such circuits.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: February 27, 2018
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Matt Allison, Eric S. Shapiro
  • Patent number: 9900004
    Abstract: An RF switching device having distributed shunt switches distributed along transmission lines to improve RF bandwidth as well as the signal isolation of the device. The shunt switches may be physically positioned on both sides of the transmission lines to keep an integrated circuit (IC) design essentially symmetrical so as to provide predictable and reliable operational characteristics. Some embodiments include stacked FET shunt switches and series switches to tolerate high voltages. In some embodiments, the gate resistor for each FET shunt switch is divided into two or more portions.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: February 20, 2018
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Jianhua Lu, Peter Bacon, Raul Inocencio Alidio, Vikram Sekar
  • Patent number: 9887695
    Abstract: A circuit and method for controlling charge injection in a circuit are disclosed. In one embodiment, the circuit and method are employed in a semiconductor-on-insulator (SOI) Radio Frequency (RF) switch. In one embodiment, an SOI RF switch comprises a plurality of switching transistors coupled in series, referred to as “stacked” transistors, and implemented as a monolithic integrated circuit on an SOI substrate. Charge injection control elements are coupled to receive injected charge from resistively-isolated nodes located between the switching transistors, and to convey the injected charge to at least one node that is not resistively-isolated. In one embodiment, the charge injection control elements comprise resistors. In another embodiment, the charge injection control elements comprise transistors.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: February 6, 2018
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Alexander Dribinsky, Tae Youn Kim, Dylan J. Kelly, Christopher N. Brindle
  • Patent number: 9887622
    Abstract: An apparatus for power conversion includes a switching network that controls interconnections between pump capacitors in a capacitor network that has a terminal coupled to a current source, and a charge-management subsystem. In operation, the switching network causes the capacitor network to execute charge-pump operating cycles during each of which the capacitor network adopts different configurations in response to different configurations of the switching network. At the start of a first charge-pump operating cycle, each pump capacitor assumes a corresponding initial state. The charge-management subsystem restores each pump capacitor to the initial state by the start of a second charge-pump operating cycle that follows the first charge-pump operating cycle.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: February 6, 2018
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Aichen Low, Gregory Szczeszynski, David Giuliano
  • Patent number: 9882471
    Abstract: An apparatus for processing electric power includes a power-converter having a path for power flow between first and second power-converter terminals. During operation the first and second power-converter terminals are maintained at respective first and second voltages. Two regulating-circuits and a switching network are disposed on the path. The first regulating-circuit includes a magnetic-storage element and a first-regulating-circuit terminal. The second regulating-circuit includes a second-regulating-circuit terminal. The first-regulating-circuit terminal is connected to the first switching-network-terminal and the second-regulating-circuit terminal is connected to the second switching-network-terminal. The switching network is transitions between a first switch-configuration and a second switch-configuration. In the first switch-configuration, charge accumulates in the first charge-storage-element at a first rate.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: January 30, 2018
    Assignee: Peregrine Semiconductor Corporation
    Inventor: David Giuliano
  • Patent number: 9882531
    Abstract: A transistor stack can include a combination of floating and body tied devices. Improved performance of the RF amplifier can be obtained by using a single body tied device as the input transistor of the stack, or as the output transistor of the stack, while other transistors of the stack are floating transistors. Transient response of the RF amplifier can be improved by using all body tied devices in the stack.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: January 30, 2018
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Simon Edward Willard, Chris Olson, Tero Tapio Ranta
  • Patent number: 9882554
    Abstract: Systems, methods, and apparatus for use in biasing and driving high voltage semiconductor devices using only low voltage transistors are described. The apparatus and method are adapted to control multiple high voltage semiconductor devices to enable high voltage power control, such as power amplifiers, power management and conversion and other applications wherein a first voltage is large compared to the maximum voltage handling of the low voltage control transistors. Timing of control signals can be adjusted via internal and/or external components so as to minimize shoot trough currents in the high voltage devices. A DC/DC power conversion implementation from high input voltage to low output voltage using a novel level shifter which uses only low voltage transistors is also provided. Also presented is a level shifter in which floating nodes and high voltage capacitive coupling and control enable the high voltage control with low voltage transistors.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: January 30, 2018
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Buddhika Abesingha, Merlin Green
  • Patent number: 9864000
    Abstract: An apparatus for detecting difference in operating characteristics of a main circuit by using a replica circuit is presented. In one exemplary case, a sensed difference in operating characteristics of the two circuits is used to drive a tuning control loop to minimize the sensed difference. In another exemplary case, several replica circuits of the main circuit are used, where each is isolated from one or more operating variables that affect the operating characteristic of the main circuit. Each replica circuit can be used for sensing a different operating characteristic, or, two replica circuits can be combined to sense a same operating characteristic.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: January 9, 2018
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Dan William Nobbe, Ronald Eugene Reedy, Peter Bacon, James S. Cable
  • Patent number: 9866212
    Abstract: An RF switch to controllably withstand an applied RF voltage Vsw, or a method of fabricating such a switch, which includes a string of series-connected constituent FETs with a node of the string between each pair of adjacent FETs. The method includes controlling capacitances between different nodes of the string to effectively tune the string capacitively, which will reduce the variance in the RF switch voltage distributed across each constituent FET, thereby enhancing switch breakdown voltage. Capacitances are controlled, for example, by disposing capacitive features between nodes of the string, and/or by varying design parameters of different constituent FETs. For each node, a sum of products of each significant capacitor by a proportion of Vsw appearing across it may be controlled to approximately zero.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: January 9, 2018
    Assignee: Peregrine Semiconductor Corporation
    Inventor: Robert Mark Englekirk
  • Patent number: 9857818
    Abstract: Systems, methods and apparatus for efficient control and biasing of pass devices driven into their triode region of operation are described. The pass devices are arranged in a cascode configuration comprising a plurality of stacked devices. Biasing of the cascode devices can be according to a voltage division scheme which provides a substantially equal voltage division across the stacked devices when the voltage across the stack is high, and provides a skewed voltage division across the stacked devices when voltage across the stack is reduced, while protecting each of the devices from overvoltage and biasing the cascoded devices for a low RON. An exemplary implementation of an LDO controlling the pass devices for providing burst RF power to a power amplifier is described.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: January 2, 2018
    Assignee: Peregrine Semiconductor Corporation
    Inventor: Jaroslaw Adamski
  • Patent number: 9851732
    Abstract: Methods and systems for electrical bias generation are disclosed. Two or more different voltage levels can be created, one above a mid-rail value and one below the mid-rail value for each pair of voltage levels. Such voltage levels can be used to power processes in other circuits by providing a safe but adequate voltage value. Transition control between an on state and an off state for a power supply can also be implemented using this bias generation.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: December 26, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventor: Robert Mark Englekirk
  • Patent number: 9847759
    Abstract: A scalable periphery tunable matching power amplifier is presented. Varying power levels can be accommodated by selectively activating or deactivating unit cells of which the scalable periphery tunable matching power amplifier is comprised. Tunable matching allows individual unit cells to see a constant output impedance, reducing need for transforming a low impedance up to a system impedance and attendant power loss. The scalable periphery tunable matching power amplifier can also be tuned for different operating conditions such as different frequencies of operation or different modes.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: December 19, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Dan William Nobbe, David Halchin, Jeffrey A. Dykstra, Michael P. Gaynor, David Kovac, Kelly Michael Mekechuk, Gary Frederick Kaatz, Chris Olson
  • Patent number: 9847715
    Abstract: A power-conversion apparatus includes active-semiconductor switches configured to transition between first and second states that result in corresponding first and second electrical interconnections between capacitors and at least one of first and second terminals configured to be coupled to first and second external circuits at corresponding first and second voltages, a pre-charge circuit coupled to at least one of the capacitors, and gate-driver circuits, each of which includes a control input, power connections, and a drive output. Each switch is coupled to and controlled by a drive output of one of the gate-driver circuits. Power for the gate-driver circuits comes from charge stored on at least one of the capacitors via the power connection of that gate-driver circuit.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: December 19, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventors: David Giuliano, Gregory Szczeszynski, Raymond Barrett, Jr.
  • Patent number: 9847348
    Abstract: Systems, methods and apparatus for coexistence of high voltage and low voltage devices and circuits on a same integrated circuit fabricated in silicon-on-insulator (SOI) technology are described. In particular, techniques for mitigating back gate effects are described, including using of resistive and/or capacitive couplings to control surface potentials at regions of a substrate used for the SOI fabrication proximate the high voltage and low voltage devices and circuits. In one case, an N-type implant is used to provide a high potential differential with respect to a substrate potential.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: December 19, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Buddhika Abesingha, Simon Edward Willard, Alain Duvallet, Merlin Green, Sivakumar Kumarasamy
  • Patent number: 9847712
    Abstract: Transient or fault conditions for a switched capacitor power converter are detected by measuring one or more of internal voltages and/or currents associated with switching elements (e.g., transistors) or phase nodes, or voltages or currents at terminals of the converter, and based on these measurements detect that a condition has occurred when the measurements deviate from a predetermined range. Upon detection of the condition fault control circuitry alters operation of the converter, for example, by using a high voltage switch to electrically disconnect at least some of the switching elements from one or more terminals of the converter, or by altering timing characteristics of the phase signals.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: December 19, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Aichen Low, David M. Giuliano, Gregory Szczeszynski, Jeff Summit, Oscar Blyde
  • Patent number: 9843293
    Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit and stacked transistors standby current during operation in the standby mode and to reduce impedance presented to the gates of the stacked transistors during operation in the active mode while maintaining voltage compliance of the stacked transistors during both modes of operation.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: December 12, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Poojan Wagh, Kashish Pal, Robert Mark Englekirk, Tero Tapio Ranta, Keith Bargroff, Simon Edward Willard
  • Patent number: 9843311
    Abstract: Systems, methods, and apparatus for use in biasing and driving high voltage semiconductor devices using only low voltage transistors are described. The apparatus and method are adapted to control multiple high voltage semiconductor devices to enable high voltage power control, such as power amplifiers, power management and conversion and other applications wherein a first voltage is large compared to the maximum voltage handling of the low voltage control transistors. A DC/DC power conversion implementation from high input voltage to low output voltage using a novel level shifter which uses only low voltage transistors is also provided. Also presented is a level shifter in which floating nodes and high voltage capacitive coupling and control enable the high voltage control with low voltage transistors.
    Type: Grant
    Filed: October 5, 2016
    Date of Patent: December 12, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Merlin Green, Mark L. Burgener, James W. Swonger, Buddhika Abesingha, Ronald Eugene Reedy
  • Patent number: 9842858
    Abstract: Systems, methods, and apparatus for an improved body tie construction are described. The improved body tie construction is configured to have a lower resistance body tie exists when the transistor is “off” (Vg approximately 0 volts). When the transistor is “on” (Vg>Vt), the resistance to the body tie is much higher, reducing the loss of performance associated with presence of body tie. Space efficient Body tie constructions adapted for cascode configurations are also described.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: December 12, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventor: Simon Edward Willard