Patents Assigned to Peregrine Semiconductor Corporation
  • Patent number: 9660598
    Abstract: Devices and methods for improving reliability of scalable periphery amplifiers is described. Amplifier segments of the scalable periphery architecture can be rotated to distribute wear. Further, extra amplifier segments can be implemented on amplifier dies to extend the overall lifetime of amplifiers.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: May 23, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventor: Chris Olson
  • Patent number: 9660590
    Abstract: A bias generation method or apparatus defined by any one or any practical combination of numerous features that contribute to low noise and/or high efficiency biasing, including: having a charge pump control clock output with a waveform having limited harmonic content or distortion compared to a sine wave; having a ring oscillator to generating a charge pump clock that includes inverters current limited by cascode devices and achieves substantially rail-to-rail output amplitude; having a differential ring oscillator with optional startup and/or phase locking features to produce two phase outputs suitably matched and in adequate phase opposition; having a ring oscillator of less than five stages generating a charge pump clock; capacitively coupling the clock output(s) to some or all of the charge transfer capacitor switches; biasing an FET, which is capacitively coupled to a drive signal, to a bias voltage via an “active bias resistor” circuit that conducts between output terminals only during portions of a wa
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: May 23, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Tae Youn Kim, Robert Mark Englekirk, Dylan J. Kelly
  • Patent number: 9660611
    Abstract: Embodiments of resonator circuits and modulating resonators and are described generally herein. One or more acoustic wave resonators may be coupled in series or parallel to generate tunable filters. One or more acoustic wave resonances may be modulated by one or more capacitors or tunable capacitors. One or more acoustic wave modules may also be switchable in a filter. Other embodiments may be described and claimed.
    Type: Grant
    Filed: May 22, 2015
    Date of Patent: May 23, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Mark L. Burgener, James S. Cable
  • Patent number: 9653601
    Abstract: A method and apparatus for use in improving linearity sensitivity of MOSFET devices having an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to address degradation in second- and third-order intermodulation harmonic distortion at a desired range of operating voltage in devices employing an accumulated charge sink.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: May 16, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Christopher N. Brindle, Jie Deng, Alper Genc, Chieh-Kai Yang
  • Patent number: 9654067
    Abstract: Device and methods for improving consistency of operation and therefore yield of scalable periphery amplifiers is described. Amplifier size of the scalable periphery architecture can be adjusted to obtain part-to-part consistency of operating performance as per a defined/desired set of criteria. Amplifier segments of the scalable periphery architecture can be rotated to distribute wear. Further, extra amplifier segments can be implemented on amplifier dies to extend the overall lifetime of amplifiers.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: May 16, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventor: Dan William Nobbe
  • Patent number: 9647631
    Abstract: A tunable impedance matching network comprising shunt (e.g. parallel) tunable capacitors and other fixed reactive elements is presented. The tunable impedance matching network can be used as one component of an SPTM (scalable periphery tunable matching) amplifier.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: May 9, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventor: Michael P. Gaynor
  • Patent number: 9640494
    Abstract: An integrated circuit (IC) structure for radio frequency circuits having a grounded die seal that mitigates the effects of parasitic coupling through the die seal. Embodiments include conductive grounding ties that each electrically couple one or more of the internal grounding pads on an IC die within the magnetic loop formed by the die seal ring to an adjacent extent of an IC die seal. Induced parasitic energy within the die seal ring is quickly coupled to ground through the corresponding grounding ties and grounding pads. Accordingly, very little, if any, induced parasitic energy is propagated around the die seal ring.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: May 2, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventor: Vikas Sharma
  • Patent number: 9634650
    Abstract: An electronic system that includes a digitally selectable phase shifter circuit and an insertion loss fine adjustment circuit such that the system as a whole exhibits little or no change in insertion loss when changing phase state, and/or a digitally selectable attenuator circuit and a phase fine adjustment circuit such that the system as a whole exhibits little or no effect on phase when changing attenuation state. Included are methods for selecting adjustment control words for such circuits.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: April 25, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Matt Allison, Eric S. Shapiro
  • Patent number: 9608619
    Abstract: A method and apparatus are disclosed for use in improving the gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one embodiment, a circuit comprises a MOSFET, operating in an accumulated charge regime, and means for controlling the accumulated charge, operatively coupled to the SOI MOSFET. A first determination is made of the effects of an uncontrolled accumulated charge on time dependent dielectric breakdown (TDDB) of the gate oxide of the SOI MOSFET. A second determination is made of the effects of a controlled accumulated charge on TDDB of the gate oxide of the SOI MOSFET.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: March 28, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Michael A. Stuber, Christopher N. Brindle, Dylan J. Kelly, Clint L. Kemerling, George P. Imthurn, Robert B. Welstand, Mark L. Burgener, Alexander Dribinsky, Tae Youn Kim
  • Patent number: 9602091
    Abstract: A wideband RF attenuator circuit that has a reduced impact on the phase of an applied signal when switched between an attenuation state and a non-attenuating reference or bypass state. A low phase shift attenuation at high RF frequencies can be achieved by utilizing a switched signal path attenuator topology with multiple distributed transmission line elements per signal path to provide broadband operation, distribute parasitic influences, and improve isolation to achieve higher attenuation at higher frequencies while still maintaining low phase shift operational characteristics. In an alternative embodiment, extension to even higher frequencies can be achieved by utilizing a quarter-wave transmission line element at the signal interfaces of each signal path, thereby improving insertion loss and power handling.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: March 21, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventor: Vikas Sharma
  • Patent number: 9602063
    Abstract: An amplifier with switchable and tunable harmonic terminations and a variable impedance matching network is presented. The amplifier can adapt to different modes and different frequency bands of operation by appropriate switching and/or tuning of the harmonic terminations and/or the variable impedance matching network.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: March 21, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Gary Frederick Kaatz, Chris Olson
  • Patent number: 9602098
    Abstract: An RF signal switch circuit that allows connection of any of N radio frequency (RF) input terminals to a switch output port, either in an in-circuit mode or in a bypass mode. Embodiments of the invention allow for both a single switch in the series input path while still having the ability to isolate the bypass path from an input matching network. In both modes, the circuit simultaneously exhibits low input insertion loss (and thus a low noise factor) and high bypass mode isolation.
    Type: Grant
    Filed: July 28, 2015
    Date of Patent: March 21, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventor: Ethan Prevost
  • Patent number: 9595956
    Abstract: An RF switch to controllably withstand an applied RF voltage Vsw, or a method of fabricating such a switch, which includes a string of series-connected constituent FETs with a node of the string between each pair of adjacent FETs. The method includes controlling capacitances between different nodes of the string to effectively tune the string capacitively, which will reduce the variance in the RF switch voltage distributed across each constituent FET, thereby enhancing switch breakdown voltage. Capacitances are controlled, for example, by disposing capacitive features between nodes of the string, and/or by varying design parameters of different constituent FETs. For each node, a sum of products of each significant capacitor by a proportion of Vsw appearing across it may be controlled to approximately zero.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: March 14, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventor: Robert Mark Englekirk
  • Patent number: 9595923
    Abstract: Methods and systems for optimizing amplifier operations are described. The described methods and systems particularly describe a feed-forward control circuit that may also be used as a feed-back control circuit in certain applications. The feed-forward control circuit provides a control signal that may be used to configure an amplifier in a variety of ways.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: March 14, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Dan William Nobbe, David Halchin
  • Patent number: 9590674
    Abstract: Semiconductor devices with switchable connection between body and a ground node are presented. Methods for operating and fabricating such semiconductor devices are also presented.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: March 7, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventor: Chris Olson
  • Patent number: 9564887
    Abstract: An absorptive switch architecture suitable for use in high frequency RF applications. A switching circuit includes a common terminal and one or more ports, any of which may be selectively coupled to the common terminal by closing an associated path switch; non-selected, unused ports are isolated from the common terminal by opening an associated path switch. Between each path switch and a port are associated shunt switches for selectively coupling an associated signal path to circuit ground. Between each path switch and a port is an associated absorptive switch module. Each absorptive switch module includes a resistor coupled in parallel with a switch. The combination of the resistor and the switch of the absorptive switch module is placed in series with a corresponding signal path from each port to the common terminal, rather than in a shunt configuration.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: February 7, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventor: Peter Bacon
  • Patent number: 9559830
    Abstract: Methods and system for using a multifunctional filter to minimize insertion loss in a multi-mode communications system are described. Specifically described is a multifunctional filter that is configurable to operate in a band-pass mode when a first type of signal is propagated through the multifunctional filter, and to operate in a low-pass mode when a second type of signal is propagated through the multifunctional filter. The multifunctional filter presents a lower insertion loss to the second type of signal when operating in the low-pass mode than in the band-pass mode.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: January 31, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventor: Dan William Nobbe
  • Patent number: 9543901
    Abstract: Optimization methods via various circuital arrangements for amplifier with variable supply power are presented. In one embodiment, a switch can be controlled to include or exclude a feedback network in a feedback path to the amplifier to adjust a response of the amplifier dependent on a region of operation of the amplifier arrangement (e.g. linear region or compression region).
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: January 10, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Dan William Nobbe, Jeffrey A. Dykstra, Chris Olson, James S. Cable
  • Patent number: 9535110
    Abstract: An apparatus for detecting an operating characteristic mismatch at an output of an amplifier by using a replica circuit is presented. In one exemplary case, a detected voltage difference at the output of the two circuits is used to drive a tuning control loop to minimize an impedance mismatch at the output of the amplifier. In another exemplary case, the replica circuit is used to detect a fault in operation in a corresponding main circuit. A method for detecting a load mismatch in a main RF circuit using the replica circuit is also presented.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: January 3, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventor: Dan William Nobbe
  • Patent number: 9537472
    Abstract: A fast response time, self-activating, adjustable threshold limiter including a limiting element LE, a first coupling element CE1 electrically connected from a signal node of LE to a control input of LE, and a second coupling element CE2 electrically connected from the control input of LE to a nominal node of LE. An initial bias (control) voltage is also supplied to the control input of LE to dynamically control the limiting threshold for the limiter. Embodiments include usage of self-activating adjustable power limiters in combination with series switch components in a switch circuit in lieu of conventional shunt switches.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: January 3, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Jianhua Lu, Peter Bacon, Naveen Yanduru, Edward Nicholas Comfoltey, Michael Conry, Chieh-Kai Yang