Patents Assigned to Peregrine Semiconductor Corporation
  • Patent number: 9755615
    Abstract: Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: September 5, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Tero Tapio Ranta, Shawn Bawell, Robert W. Greene, Christopher N. Brindle, Robert Mark Englekirk
  • Patent number: 9729107
    Abstract: Various envelope tracking amplifiers are presented that can be switched between an ET (envelope tracking) mode and a non-ET mode. Switches and/or tunable components are utilized in constructing the envelope tracking amplifiers that can be switched between the ET mode and the non-ET mode.
    Type: Grant
    Filed: August 7, 2015
    Date of Patent: August 8, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Dan William Nobbe, Jeffrey A. Dykstra, Chris Olson, James S. Cable
  • Patent number: 9716477
    Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are presented, where the amplifier can be an envelope tracking amplifier. Circuital arrangements to generate reference gate-to-source voltages for biasing of the gates of the transistors of the stack are also presented. Particular biasing for a case of an input transistor of the stack is also presented.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: July 25, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Poojan Wagh, Joseph Golat, David Kovac, Jeffrey A. Dykstra, Chris Olson
  • Patent number: 9716475
    Abstract: A selectable low noise amplifier (LNA) system comprising, a plurality of LNAs having a plurality of LNA characteristics and at least one selection switch network coupled to the plurality of LNAs to select at least one of the plurality of LNAs.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: July 25, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventor: Hossein Noori
  • Patent number: 9717008
    Abstract: A calibration architecture that enables accurate calibration of radio frequency (RF) integrated circuits (ICs) chips used in multi-transceiver RF systems in a relatively simple testing environment. Embodiments of the invention include one or more on-chip switchable cross-circuit calibration paths that enable direct coupling of a portion of the on-chip circuit to an RF test system while isolating other circuitry on the chip. Periodic self-calibration of an RF IC can be performed after initial factory calibration, so that adjustments in desired performance parameters can be made while such an IC is embedded within a final system, and/or to take into account component degradation due to age or other factors.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: July 25, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventor: Vikas Sharma
  • Patent number: 9712120
    Abstract: Methods and systems for optimizing amplifier operations are described. The described methods and systems particularly describe a feed-forward control circuit that may also be used as a feed-back control circuit in certain applications. The feed-forward control circuit provides a control signal that may be used to configure an amplifier in a variety of ways.
    Type: Grant
    Filed: July 8, 2015
    Date of Patent: July 18, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Dan William Nobbe, David Halchin
  • Patent number: 9712160
    Abstract: A FET-based RF switch architecture and method that provides for independent control of FETs within component branches of a switching circuit. With independent control of branch FETs, every RF FET in an inactive branch that is in an “open” (capacitive) state can be shunted to RF ground and thus mitigate impedance mismatch effects. Providing a sufficiently low impedance to RF ground diminishes such negative effects and reduces the sensitivity of the switch circuit to non-matched impedances.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: July 18, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Michael Conry, Kevin Roberts, Edward Nicholas Comfoltey
  • Patent number: 9709620
    Abstract: A sense circuit and method for use in measuring the blown or unblown state of fusible links (fuses), particularly in integrated circuits. Embodiments include at least one additional reference resistance to allow for a greater margin of error in determining the actual state of a fuse. By having two or more reference resistances that can be independently selectable, additional combinations of reference resistance values are available to compare against the resistance of a fuse being tested.
    Type: Grant
    Filed: September 17, 2014
    Date of Patent: July 18, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventor: Robert Mark Englekirk
  • Patent number: 9705482
    Abstract: A high voltage input buffer having a first transistor having a first drain, a first source and a first gate configured to receive an input signal and a second transistor having a second drain, a second source and a second gate, wherein the second source is coupled to the first source to form an output, the second gate is coupled to the first drain and the second drain is coupled to the first gate and wherein when the input signal is less than a high voltage power on the first drain an output signal at the output follows the input signal and when the input signal is greater than the high voltage power on the first drain the output follows the high voltage power and a hysteretic circuit adapted to receive the output signal.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: July 11, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventor: Robert Mark Englekirk
  • Patent number: 9698752
    Abstract: Embodiments of resonator circuits and modulating resonators and are described generally herein. One or more acoustic wave resonators may be coupled in series or parallel to generate tunable filters. One or more acoustic wave resonances may be modulated by one or more capacitors or tunable capacitors. One or more acoustic wave modules may also be switchable in a filter. Other embodiments may be described and claimed.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: July 4, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Mark L. Burgener, James S. Cable
  • Patent number: 9685990
    Abstract: Methods and devices are described for overcoming insertion loss notches in RF systems. In one case programmable impedances are used to move an insertion loss notch outside a frequency band of interest.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: June 20, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventor: Kevin Roberts
  • Patent number: 9685946
    Abstract: An RF switching device having distributed shunt switches distributed along transmission lines to improve RF bandwidth as well as the signal isolation of the device. The shunt switches may be physically positioned on both sides of the transmission lines to keep an integrated circuit (IC) design essentially symmetrical so as to provide predictable and reliable operational characteristics. Some embodiments include stacked FET shunt switches and series switches to tolerate high voltages. In some embodiments, the gate resistor for each FET shunt switch is divided into two or more portions.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: June 20, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Jianhua Lu, Peter Bacon, Raul Inocencio Alidio, Vikram Sekar
  • Patent number: 9685963
    Abstract: A charge pump circuit that utilizes a sensing circuit for determining the current loading or status of the output supply generated by the charge pump circuit to determine a corresponding frequency for a variable rate clock for the charge pump circuit. When a current load is present, the clock frequency automatically ramps up to a relatively high level to increase the output current of the charge pump circuit. When the current load is removed and the supply is settled out, the clock frequency is automatically reduced to a relatively quieter level and the charge pump circuitry operates at a lower power level. Accordingly, the charge pump circuit is only noisy when it has to be, thus providing optimal power when required and being electrically quiet and operating at lower power at all other times.
    Type: Grant
    Filed: January 8, 2016
    Date of Patent: June 20, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventor: Robert Mark Englekirk
  • Patent number: 9680416
    Abstract: A monolithic integrated circuit (IC), and method of manufacturing same, that includes all RF front end or transceiver elements for a portable communication device, including a power amplifier (PA), a matching, coupling and filtering network, and an antenna switch to couple the conditioned PA signal to an antenna. An output signal sensor senses at least a voltage amplitude of the signal switched by the antenna switch, and signals a PA control circuit to limit PA output power in response to excessive values of sensed output. Stacks of multiple FETs in series to operate as a switching device may be used for implementation of the RF front end, and the method and apparatus of such stacks are claimed as subcombinations. An iClass PA architecture is described that dissipatively terminates unwanted harmonics of the PA output signal.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: June 13, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Mark L. Burgener, James S. Cable
  • Patent number: 9673155
    Abstract: An apparatus and method for a frequency based integrated circuit that selectively filters out unwanted bands or regions of interfering frequencies utilizing one or more tunable notch or bandpass filters or tunable low or high pass filters capable of operating across multiple frequencies and multiple bands in noisy RF environments. The tunable filters are fabricated within the same integrated circuit package as the associated frequency based circuitry, thus minimizing R, L, and C parasitic values, and also allowing residual and other parasitic impedance in the associated circuitry and IC package to be absorbed and compensated.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: June 6, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventors: William R. Smith, Jaroslaw Adamski, Dan William Nobbe, Edward Nicholas Comfoltey, Jingbo Wang
  • Patent number: 9667195
    Abstract: Various envelope tracking amplifiers are presented that can be switched between an ET (envelope tracking) mode and a non-ET mode. Switches and/or tunable components are utilized in constructing the envelope tracking amplifiers that can be switched between the ET mode and the non-ET mode.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: May 30, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Dan William Nobbe, Jeffrey A. Dykstra, Chris Olson, James S. Cable
  • Patent number: 9667217
    Abstract: A high performance integrated tunable impedance matching network with coupled merged inductors. Embodiments include a combination of merged multiport constructively coupled spiral inductors and tunable capacitors configured to reduce insertion losses, circuit size, and optimization time while maintaining a high Q factor for the coupled spiral inductors.
    Type: Grant
    Filed: April 17, 2015
    Date of Patent: May 30, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Chih-Chieh Cheng, Tero Tapio Ranta, Richard Bryon Whatley, Vikram Sekar
  • Patent number: 9667246
    Abstract: A switch architecture having open reflective unselected ports. Signals can be selectively coupled between a common port and at least one selectable port through series connected switches. When one or more port is selected, the remaining ports are opened. In addition, associated “shuntable” switches from each of the selectable ports to ground are always open, regardless of the ON or OFF state of the series switches; thus, there is no normally active connection of the selectable ports to ground, but the presence of the shuntable switches provides electrostatic discharge protection for all ports. Embodiments of the invention allow configurability between a traditional architecture and an open reflective unselected port architecture, and include integrated circuit and field effect transistor embodiments.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: May 30, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Tero Tapio Ranta, Chih-Chieh Cheng
  • Patent number: 9667227
    Abstract: A method and apparatus for use in a digitally tuning a capacitor in an integrated circuit device is described. A Digitally Tuned Capacitor DTC is described which facilitates digitally controlling capacitance applied between a first and second terminal. In some embodiments, the first terminal comprises an RF+ terminal and the second terminal comprises an RF? terminal. In accordance with some embodiments, the DTCs comprise a plurality of sub-circuits ordered in significance from least significant bit (LSB) to most significant bit (MSB) sub-circuits, wherein the plurality of significant bit sub-circuits are coupled together in parallel, and wherein each sub-circuit has a first node coupled to the first RF terminal, and a second node coupled to the second RF terminal. The DTCs further include an input means for receiving a digital control word, wherein the digital control word comprises bits that are similarly ordered in significance from an LSB to an MSB.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: May 30, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventor: Tero Tapio Ranta
  • Patent number: 9667255
    Abstract: Circuits and corresponding methods that provide for selection among multiple different positive and/or multiple different negative FET gate drive voltages for FETs in which well-tuned gate drive voltages are needed or desirable for optimal results in a radio frequency integrated circuit. Embodiments include FET gate drive variable voltage generator configurations which provide multiple different positive and/or multiple different negative FET gate drive voltages. In alternative embodiments, an IC may include multiple positive voltage generators and/or multiple negative voltage generators, each voltage generator providing an output voltage different from at least one other voltage generator. The voltage generators include charge pump based circuits and digital-to-analog converters. Each FET device requiring a well-tuned gate drive voltage is selectably coupled to at least one set of positive and negative voltage generators.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: May 30, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventor: Robert Mark Englekirk