Patents Assigned to Peregrine Semiconductor Corporation
  • Patent number: 8441299
    Abstract: Dual path level shifter methods and devices are described. The described level shifter devices can comprise voltage-to-current and current-to-voltage converters.
    Type: Grant
    Filed: January 28, 2010
    Date of Patent: May 14, 2013
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Chris Olson, Neil Calanca
  • Patent number: 8410840
    Abstract: Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: April 2, 2013
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Tero Tapio Ranta, Shawn Bawell, Robert W. Greene, Christopher N. Brindle, Robert Mark Englekirk
  • Patent number: 8405147
    Abstract: A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOT MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: March 26, 2013
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Christopher N. Brindle, Michael A. Stuber, Dylan J. Kelly, Clint L. Kemerling, George P. Imthurn, Robert B. Welstand, Mark L. Burgener
  • Patent number: 8378736
    Abstract: A charge pump method and apparatus is described having various aspects. Noise injection from a charge pump to other circuits may be reduced by limiting both positive and negative clock transition rates, as well as by limiting drive currents within clock generator driver circuits, and also by increasing a control node AC impedance of certain transfer capacitor coupling switches. A single-phase clock may be used to control as many as all active switches within a charge pump, and capacitive coupling may simplify biasing and timing for clock signals controlling transfer capacitor coupling switches. Any combination of such aspects of the method or apparatus may be employed to quiet and/or simplify charge pump designs over a wide range of charge pump architectures.
    Type: Grant
    Filed: April 27, 2010
    Date of Patent: February 19, 2013
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Mark L. Burgener, Dylan J. Kelly, James S. Cable
  • Patent number: 8373490
    Abstract: Embodiments of RF and DC switching are described generally herein. Other embodiments may be described and claimed.
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: February 12, 2013
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Mark L. Burgener, Fleming Lam
  • Patent number: 8368462
    Abstract: Embodiments of RF switching amplifiers are described generally herein. Other embodiments may be described and claimed.
    Type: Grant
    Filed: October 6, 2010
    Date of Patent: February 5, 2013
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Vikas Sharma, Jaroslaw Adamski, Neil Calanca, Robert Broughton
  • Patent number: 8350624
    Abstract: Biasing methods and devices for amplifiers are described. The described methods generate bias voltages proportional to the amplifier output voltage to control stress voltages across transistors used within the amplifier.
    Type: Grant
    Filed: September 1, 2010
    Date of Patent: January 8, 2013
    Assignee: Peregrine Semiconductor Corporation
    Inventor: Fleming Lam
  • Patent number: 8330504
    Abstract: Dynamic biasing methods and circuits are described. The described methods generate bias voltages that are continuously varied so as to control stress voltages across transistors used within a cascode stack.
    Type: Grant
    Filed: February 4, 2011
    Date of Patent: December 11, 2012
    Assignee: Peregrine Semiconductor Corporation
    Inventor: Chris Olson
  • Patent number: 8305139
    Abstract: Driver circuits and methods related thereto for driving high power and/or high frequency devices are described. The driver circuits comprise transistor stacks and capacitors coupled with the transistor stacks. Voltages across the capacitors depend on state (on or off) of each transistor in the transistor stacks. These voltages in turn determine output voltages generated by the driver circuits.
    Type: Grant
    Filed: October 5, 2011
    Date of Patent: November 6, 2012
    Assignee: Peregrine Semiconductor Corporation
    Inventor: Jeffrey A. Dykstra
  • Patent number: 8143935
    Abstract: A circuit and method for controlling charge injection in a circuit are disclosed. In one embodiment, the circuit and method are employed in a semiconductor-on-insulator (SOI) Radio Frequency (RF) switch. In one embodiment, an SOI RF switch comprises a plurality of switching transistors coupled in series, referred to as “stacked” transistors, and implemented as a monolithic integrated circuit on an SOI substrate. Charge injection control elements are coupled to receive injected charge from resistively-isolated nodes located between the switching transistors, and to convey the injected charge to at least one node that is not resistively-isolated. In one embodiment, the charge injection control elements comprise resistors. In another embodiment, the charge injection control elements comprise transistors.
    Type: Grant
    Filed: July 26, 2007
    Date of Patent: March 27, 2012
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Alexander Dribinsky, Tae Youn Kim, Dylan J. Kelly, Christopher N. Brindle
  • Patent number: 8131251
    Abstract: A monolithic integrated circuit (IC), and method of manufacturing same, that includes all RF front end or transceiver elements for a portable communication device, including a power amplifier (PA), a matching, coupling and filtering network, and an antenna switch to couple the conditioned PA signal to an antenna. An output signal sensor senses at least a voltage amplitude of the signal switched by the antenna switch, and signals a PA control circuit to limit PA output power in response to excessive values of sensed output. Stacks of multiple FETs in series to operate as a switching device may be used for implementation of the RF front end, and the method and apparatus of such stacks are claimed as subcombinations. An iClass PA architecture is described that dissipatively terminates unwanted harmonics of the PA output signal.
    Type: Grant
    Filed: August 7, 2006
    Date of Patent: March 6, 2012
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Mark L. Burgener, James S. Cable
  • Patent number: 8129787
    Abstract: A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: March 6, 2012
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Christopher N. Brindle, Michael A. Stuber, Dylan J. Kelly, Clint L. Kemerling, George P. Imthurn, Robert B. Welstand, Mark L. Burgener
  • Patent number: 8130042
    Abstract: Methods and devices for leakage current reduction are described. A regulator transistor is connected to a switch to bias the transistor with a first voltage during an ON state and a second voltage during the OFF state of the transistor. The switchable bias allows leakage current decrease and “on” resistance increase of the transistor.
    Type: Grant
    Filed: May 3, 2010
    Date of Patent: March 6, 2012
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Jaroslaw Adamski, Daniel Losser, Vikas Sharma
  • Patent number: 8111104
    Abstract: Biasing methods and devices for power amplifiers are described. The described methods and devices use the power amplifier output voltage to generate bias voltages. The bias voltages are obtained using rectifiers and voltage dividers. The described biasing methods and devices can be used with class-E power amplifiers.
    Type: Grant
    Filed: January 25, 2010
    Date of Patent: February 7, 2012
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Joseph F. Ahadian, Vikas Sharma, Neil Calanca, Jaroslaw E. Adamski
  • Patent number: 8081928
    Abstract: An RF switching circuit adapted to cancel selected harmonic signals. An unwanted harmonic signal Sh1 at a selected harmonic frequency Fsh of an operating frequency Fo exists in a signal Si conducted by the switching circuit, possibly produced by the switching circuit due to conduction through a first nonlinear impedance Znl(1). A compensating harmonic signal Sh2 is therefore generated by conduction via a nonlinear impedance Znl(2). Znl(1) may be due to parasitic conduction by “off” switching elements, while Znl(2) may be due to conduction by an “on” FET. The amplitude and/or phasing of Sh2 may be adjusted by selecting components for a network coupling Znl(2) to the conducted signal Si, such that Sh2 substantially cancels Sh1 across a target range of input power.
    Type: Grant
    Filed: February 3, 2006
    Date of Patent: December 20, 2011
    Assignee: Peregrine Semiconductor Corporation
    Inventor: Dylan J. Kelly
  • Patent number: 8022734
    Abstract: A power detection system is disclosed that includes a detector circuit and a comparator circuit. The detector circuit includes a first transistor, a second transistor that is not identical to the first transistor, and a third transistor that is substantially identical to the first transistor. Each of the transistors is commonly coupled to a current source and is coupled to a differential input voltage. The comparator circuit is for providing an output that is representative of whether the input voltage is above or below a threshold voltage responsive to a difference between the first transistor and the second transistor.
    Type: Grant
    Filed: August 25, 2008
    Date of Patent: September 20, 2011
    Assignee: Peregrine Semiconductor Corporation
    Inventor: Robert Broughton
  • Patent number: 7961052
    Abstract: A novel RF power amplifier integrated circuit (PA IC), unit cell, and method for amplifying RF signals are disclosed. One embodiment of a PA IC includes at least two linear arrays comprising transistor device units, and at least one linear array comprising capacitors. The transistor device units include source nodes that are jointly coupled to a source bus, and selected gate nodes that are jointly coupled to a gate bus. First electrodes of the capacitors are also jointly coupled to the source bus, and second electrodes of the capacitors are jointly coupled to the gate bus. Each linear array comprising capacitors is disposed between at least two linear arrays comprising transistor device units. In one embodiment, the PA IC includes unit cells. In some embodiments, each unit cell comprises two transistor device units and one or more capacitors. The capacitors are disposed between the transistor device units.
    Type: Grant
    Filed: October 28, 2009
    Date of Patent: June 14, 2011
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Peter Bacon, Robert Broughton, Yang Li, James Bonkowski, Neil Calanca
  • Patent number: 7960772
    Abstract: An RF switch to controllably withstand an applied RF voltage Vsw, or a method of fabricating such a switch, which includes a string of series-connected constituent FETs with a node of the string between each pair of adjacent FETs. The method includes controlling capacitances between different nodes of the string to effectively tune the string capacitively, which will reduce the variance in the RF switch voltage distributed across each constituent FET, thereby enhancing switch breakdown voltage. Capacitances are controlled, for example, by disposing capacitive features between nodes of the string, and/or by varying design parameters of different constituent FETs. For each node, a sum of products of each significant capacitor by a proportion of Vsw appearing across it may be controlled to approximately zero.
    Type: Grant
    Filed: April 26, 2007
    Date of Patent: June 14, 2011
    Assignee: Peregrine Semiconductor Corporation
    Inventor: Robert Mark Englekirk
  • Patent number: 7937062
    Abstract: A monolithic integrated circuit (IC), and method of manufacturing same, that includes all RF front end or transceiver elements for a portable communication device, including a power amplifier (PA), a matching, coupling and filtering network, and an antenna switch to couple the conditioned PA signal to an antenna. An output signal sensor senses at least a voltage amplitude of the signal switched by the antenna switch, and signals a PA control circuit to limit PA output power in response to excessive values of sensed output. Stacks of multiple FETs in series to operate as a switching device may be used for implementation of the RF front end, and the method and apparatus of such stacks are claimed as subcombinations. An iClass PA architecture is described that dissipatively terminates unwanted harmonics of the PA output signal.
    Type: Grant
    Filed: August 7, 2006
    Date of Patent: May 3, 2011
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Mark L. Burgener, James S. Cable
  • Patent number: 7910993
    Abstract: A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.
    Type: Grant
    Filed: July 10, 2006
    Date of Patent: March 22, 2011
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Christopher N. Brindle, Michael A. Stuber, Dylan J. Kelly, Clint L. Kemerling, George P. Imthurn, Robert B. Welstand, Mark L. Burgener