Abstract: A package structure with embedded chip and a fabrication method thereof are proposed. A carrier board is provided, and at least one semiconductor chip is mounted on the carrier board. A core board having a cavity corresponding in position to the semiconductor chip and an insulating layer are pressed on the carrier board, such that the semiconductor chip is received in the cavity of the core board, and the insulating layer is filled in a gap between the cavity of the core board and the semiconductor chip so as to fix the semiconductor chip in the cavity. A circuit patterning process is performed on the insulating layer to form a circuit layer electrically connected to the semiconductor chip. A passive component can be mounted in the core board and electrically connected to the circuit layer. Thereby, the fabrication of a chip carrier and the chip packaging process are integrated.

Abstract: A heat sink structure with embedded electronic components is proposed, wherein a plurality of recessed cavities are formed on a heat sink for embedding the electronic components and receiving at least one semiconductor chip therein. This arrangement enhances electric performance of a semiconductor package with the above heat sink structure and improves heat dissipating efficiency of the semiconductor package.

Abstract: A method for fabricating a semiconductor package substrate having a plated metal layer on a conductive pad is proposed. First of all, a first resist layer is formed on a semiconductor package substrate having a plurality of traces and conductive pads on a surface thereof. The first resist layer is provided with at least an opening, such that the opening is able to contact the adjacent trace. Subsequently, a conductive film is formed in the opening, such that the conductive film can electrically connect the adjacent trace and conductive pad. After removing the first resist layer, a second resist layer having a plurality of openings is formed on the surface of the substrate to expose the conductive pad. Afterwards, an electroplating process is performed on the substrate, so that a metal layer is formed on an exposed surface of the conductive pad. The second resist layer and the conductive film are then removed from the substrate.

Abstract: A method of embedding a semiconductor element in a carrier and an embedded structure thereof are proposed. First, a carrier having a hole is provided and an auxiliary material is attached to a side of the carrier. A semiconductor element is placed in the hole of the carrier. Then, a medium material and glue are applied in order in the hole to firmly position the semiconductor element in the hole of the carrier via the glue. Finally, the auxiliary material and the medium material are removed to form a structure with the semiconductor element being embedded in the carrier, thereby eliminating the drawbacks encountered in packing the semiconductor element in the prior art.

Abstract: A circuit barrier structure of a semiconductor packaging substrate and a method for fabricating the same, forming a metal conductive layer on an insulating layer of the substrate and a patterned resist layer on the metal conductive layer. The patterned resist layer has a plurality of holes to expose predetermined parts of the metal conductive layer. A metal barrier layer is formed on the resist layer and in the holes. A patterned circuit layer is electroplated in the holes of the resist layer after removing the metal barrier layer on the resist layer. The resist layer and the metal conductive layer underneath the resist layer are removed. Another metal barrier layer can be formed on the circuit layer. The patterned circuit layer is covered by the metal barrier layers to prevent damage from etching to the circuit layer and inhibit migration of metal particles in the circuit layer.

Abstract: A substrate structure integrated with passive components is proposed. The substrate structure includes a carrier plate and a plurality of passive components provided on the carrier plate. The carrier plate is formed with at least one cavity for receiving the passive components and at least one opening for receiving electronic elements. Further, a heat sink can be attached to the carrier plate to improve the heat dissipation efficiency. An insulating layer with circuit structures can be formed on the carrier plate to modularize the substrate structure, so as to provide a desirable electrical design of semiconductors carried by the substrate structure.

Abstract: A method of plating a metal layer over isolated pads on a semiconductor package substrate is proposed. This substrate is formed with a plurality of conductive blind vias. The isolated pads are formed on a surface of the substrate, each having a plating line extending towards one blind via but electrically insulated from the blind via by an electrically insulating region. A conductive film covers the surface of the substrate having the isolated pads, and a photoresist layer is formed over the conductive film. The photoresist layer has openings for exposing a portion of the conductive film covering the isolated pads. The exposed portion of the conductive film is removed, to allow a metal layer to be plated on the isolated pads. Then, the photoresist layer and the remainder of the conductive film are removed, and the electrical insulation between the isolated pads and the blind vias is restored.

Abstract: A method for fabricating a core circuit board having passive components, such as resistors, capacitors and inductors, is disclosed, which can be used to construct a multilayer circuit board having embedded passive components. In making such as a core circuit board, a resistive film which is a continuous or non-continuous is first formed on one side of a conductive foil. Two such conductive foils are laminated onto a high dielectric layer. The electrodes for various passive components or spiral coils for the inductive components and electrical circuit pattern are finally made on the same conductive foils simultaneously. Finally, a core circuit board having passive components for further making a multilayer circuit board is thus constructed.

Abstract: The present invention discloses a substrate within a Ni/Au structure electroplated on electrical contact pads and a method for fabricating the same. The method comprises: providing a substrate with a circuit layout pattern and forming a conducting film on the surface of the substrate; depositing a first photoresist layer within an opening on said electrical conducting film surface to expose a portion of said circuit layout pattern to be electrical contact pads; removing the exposed conducting film uncovered by the first photoresist layer; depositing a second photoresist layer, covering the conducting film exposed in the openings of the first photoresist layer; electroplating Ni/Au covering the surface of the electrical contact pads; removing the first and second photoresists, and the conducting film covered by the photoresists; depositing solder mask on the substrate within an opening to expose said electrical contact pads.

Abstract: A substrate with stacked vias and fine circuits and a method for fabricating the substrate are proposed. A core layer is formed with a metal layer respectively on upper and lower surfaces thereof, and at least one through hole. A first insulating layer is applied over the metal layer on the upper surface of the core layer and selectively formed with at least one first opening for exposing the metal layer. A metal layer is formed within the first opening, and a second insulating layer is applied over the first insulating layer and formed with a plurality of second openings, wherein the metal layer within the first opening is exposed via at least one second opening. After a conductive layer is applied over the second insulating layer and within the second openings, a metal layer is formed within the second openings. Finally, the conductive layer is removed by micro-etching.

Abstract: Disclosed is a method for fabricating vias in solder pads of a ball grid array (BGA) substrate. The substrate is drilled to form the plural vias, and then the interior surfaces of said vias are plated with a copper layer for forming the electrically conductive vias. After the high solid content of the resin is adopted for being plugged into the electrically conductive vias, the both ends of the electrically conductive vias and the upper surface and the lower surface of the substrate are plated with a copper layer. Then said copper layers are etched to form the upper circuit layer and the lower circuit layer and the solder pads. The method in present invention can increase the density of the circuits. Because the both ends of the electrically conductive vias plugged with the resin are very planar, it can be made use of forming a core layer for the built-up fabrication.

Abstract: The present invention discloses a substrate within a Ni/Au structure electroplated on electrical contact pads and a method for fabricating the same. The method comprises: providing a substrate with a circuit layout pattern and forming a conducting film on the surface of the substrate; depositing a first photoresist layer within an opening on said electrical conducting film surface to expose a portion of said circuit layout pattern to be electrical contact pads; removing the exposed conducting film uncovered by the first photoresist layer; depositing a second photoresist layer, covering the conducting film exposed in the openings of the first photoresist layer; electroplating Ni/Au covering the surface of the electrical contact pads; removing the first and second photoresists, and the conducting film covered by the photoresists; depositing solder mask on the substrate within an opening to expose said electrical contact pads.

Abstract: A method for producing bumps on an IC package substrate. The method first deposits a medium layer on a protective layer of the IC package substrate, which has good adherence ability to both the copper layer and the protective layer. Then, a CVD process is applied to deposit a copper layer on the medium layer to form the metal layer. A dry film is thereafter formed on the metal layer and several contact windows are opened therein. A metal pad and a bump are electroplated in the contact windows. Then the dry film is removed, the bumps are protruded out of the substrate with a predetermined height to be solder bumps with an IC chip. Thus, an IC chip no longer needs to form bumps thereon anymore and to save cost and reduce pitch between bumps down to 150 um. Therefore, the improved BGA substrate may be applied on to smaller IC package device to meet the trend for minimizing package sizes.

Abstract: Disclosed is a method of preparing a thin core substrate for fabricating a build-up multilayer circuit board. The method involves the use of an insulating layer which is covered with the electrically conductive sheets. The openings are made in the electrically conductive layers at the predetermined positions, where the vias are also formed in the insulating layer. An electrically conductive layer is deposited to cover the vias. After the electrically conductive sheets and layer are patterned, a thin core substrate is constructed. The build-up layers are then made at least one side of the thin core substrate to form a build-up multilayer circuit board.

Abstract: The present invention discloses a substrate within a Ni/Au structure electroplated on electrical contact pads and a method for fabricating the same. The method comprises: providing a substrate with a circuit layout pattern and forming a conducting film on the surface of the substrate; depositing a first photoresist layer within an opening on said electrical conducting film surface to expose a portion of said circuit layout pattern to be electrical contact pads; removing the exposed conducting film uncovered by the first photoresist layer; depositing a second photoresist layer, covering the conducting film exposed in the openings of the first photoresist layer; electroplating Ni/Au covering the surface of the electrical contact pads; removing the first and second photoresists, and the conducting film covered by the photoresists; depositing solder mask on the substrate within an opening to expose said electrical contact pads.

Abstract: A pin attachment method for mounting the pins on a wiring substrate for fabricating a pin grid array package is disclosed. There is provided an organic wiring board including a surface bearing electrical circuitry which includes at least one contact pad for receiving a pin. A solder mask layer which is placed on the board surface and patterned to expose the pad. The solder mask layer which does not cover any portion of the pad and forms a well by the perimeter of the solder mask layer around the pad. Subsequently, a pin and a solder material which are placed over said pad in the well. The pin which is soldered to the pad by a temperature sufficient to melt the solder material.

Abstract: BGA substrate with direct heat dissipating structure The present invention discloses a structure of BGA substrate with direct heat-dissipating structure, said structure comprising: a heat spreader, no less than one insulating resin layer, an upper circuit layer, a lower circuit layer, and a plurality of electrically-conducting plugs. The heat spreader comprises a body part, a loading part, and a junction part. The loading part is the upper region of heat spreader. The junction part is the lower region of the heat spreader. The periphery of said junction part extends outward for forming a protruding edge. The body part is embedded into the central region of the substrate. The upper circuit layer is formed on the surface of said resin layer. The lower circuit layer is formed on lower surface of said resin layer and comprises a plurality of solder pads. The upper and lower circuit layers are conducted by electrically conductive plugs.

Abstract: A stiff heat spreader element for making a cavity down plastic chip carrier having benefits of excellent heat dissipation property, low weight, small thickness, low warpage and low twist is disclosed. The stiff heat spreader element is formed by bonding a heat spreader and a thermally conductive sheet with using a first bonding sheet. The first bonding sheet is a prepreg or prepregs made of fiber-reinforced resin. A second bonding sheet is used to bond a circuit substrate and the stiff heat spreader element. The second bonding sheet is made of a single adhesive layer or a stack of adhesive layers. The adhesive layer is made of an adhesive material, or a flake-filled adhesive material, or short fiber-filled adhesive material, or a particle-filled adhesive material. The second bonding sheet is not a prepreg or prepregs. The circuit substrate has an opening to receive an electronic chip.

Abstract: Disclosed is a structure of substrate and a fabricating method for IC (integrated circuit) chip package. Selected areas of the copper plate are etched for forming the plural conducting columns, and then an insulating layer is laminated to said copper plate to make said conducting columns embedded into said insulating layer. After portions of said insulating layer are removed for forming the plural blind vias each corresponding to exposed conducting columns, both said plural blind vias and the upper surface of said insulating layer are plated with a copper layer. An upper circuit layer and a lower circuit layer formed by etching said copper layer and said copper plate are covered with solder mask layers for protecting the substrate.

Abstract: A printer employing a scanning electrostatic print head includes a sensor to determine dimensional variations in a printable dielectric material, such as paper, on which a latent electrostatic image is disposed. A charge deposition delay circuit is in electrical communication with the scanning print head which allows properly positioning the electrostatic image on the dielectric material to compensate for the dimensional variations.