Abstract: Carrier structure embedded with semiconductor chips and method for manufacturing the same are disclosed. The carrier structure comprises a metal plate and pluralities of semiconductor chips. An adhesive material is disposed on both surfaces of the metal plate, and pluralities of cavities are formed through the metal plate. The semiconductor chips are embedded in the cavities and mounted in the metal plate. The semiconductor chips each have an active surface on which pluralities of electrode pads are disposed. A built-up structure is formed on the surface of the carrier structure and the active surfaces of the semiconductor chips, which has pluralities of conductive vias therein to conduct the semiconductor chips, and has pads thereon. Besides, the metal plate has an etching cavity between the semiconductor chips, and the etching cavity is filled with the adhesive material. The present invention solves the problem of metal burrs being formed when cutting.

Abstract: A circuit board structure with an embedded semiconductor element and a fabrication method thereof are disclosed according to the present invention. The circuit board structure comprises: a carrier board having a first surface, a second surface, and at least one through hole penetrating the carrier board from the first surface to the second surface; a first semiconductor element received in the through hole and having an active surface and an inactive surface, the active surface having a plurality of electrode pads; at least one second semiconductor element mounted on the carrier board; a first encapsulation layer formed on the first surface of the carrier board to block one end of the through hole; and a second encapsulation layer formed on the second surface of the carrier board.

Abstract: The invention provides a printed circuit board having an embedded semiconductor chip, includes: a carrier board having a first and an opposing second surface and a through hole penetrating the first and second surfaces; a semiconductor chip disposed in the through hole and having an active surface and an inactive surface, wherein the active surface includes a plurality of electrode pads; at least one non photoimagable laminating layer formed on the first surface of the carrier board and with a through hole to expose the inactive surface of the semiconductor chip; a dielectric layer and a circuit layer formed on the second surface of the carrier board and the active surface of the semiconductor chip, wherein the circuit layer electrically connects to the electrode pads of the semiconductor chip, thereby preventing the carrier board from warpage due to temperature variations and an asymmetric structure during a single-side circuit formation process of the carrier board.

Abstract: The invention provides a method for fabricating printed circuit board having an embedded semiconductor chip, including: providing a carrier board including a first and a second surface and at least one through hole penetrating the first and second surfaces; disposing a semiconductor chip in the through hole and including an active surface and an inactive surface, the active surface including a plurality of electrode pads; forming at least one non photoimagable laminating layer on the first surface of the carrier board with a through hole to expose the inactive surface of the semiconductor chip; forming a dielectric layer on the second surface of the carrier board and the active surface of the semiconductor chip; and forming a circuit layer on the dielectric layer, the circuit layer electrically connecting to the electrode pads of the semiconductor chip through conductive structures in the dielectric layer, thereby preventing the carrier board from warpage due to temperature variations and an asymmetric struct

Abstract: A flip chip substrate comprises a substrate that is defined a chip connect zone which has a plurality of first conductive pads and passive component connect zone which has at least a second conductive pads. A first patterned insulating layer within opening that covers on the chip connect zone and exposed to the first conductive pads, a second patterned insulating layer within opening that covers on the passive component connect zone and exposed to the second conductive pads, to enhance the reliability of chip package.

Abstract: The package substrate of the present invention comprises a carrying board, bump pads, wire bonding pads, a solder mask, metallic bumps, and a metallic protective layer. The solder pads and the wire bonding pads are disposed on the surface of the carrying board. The solder mask is patterned to expose bump pads, wire bonding pads, and part of the surface of the substrate on the periphery of the wire bonding pads. The metallic bumps are disposed on the surface of the bump pads and extend to the surface of the solder mask. The metallic protective layer is disposed on the surfaces of the metallic bumps and the wire bonding pads. Besides, a method for manufacturing this package substrate, a semiconductor package structure comprising this package substrate, and a manufacturing method thereof are disclosed. Therefore, the manufacturing process of the package substrate is simple, and the package substrate is slim.

Abstract: A metal electroplating process of an electrically connecting pad structure of a circuit board and structure thereof are proposed. First, a circuit board with a patterned circuit layer formed on at least one surface thereof is provided, wherein the circuit layer defines a plurality of electrically connecting pads and electroplating lines connected to the electrically connecting pads. Then, a patterned resist layer is formed on the circuit layer of the circuit board with the electroplating lines being covered by the patterned resist layer and the electrically connecting pads being exposed from the patterned resist layer. Subsequently, an electroplating process is performed so as to form a metal protection layer on the electrically connecting pads exposed from the patterned resist layer. Then, the resist layer is removed and a solder mask layer is formed on the circuit board.

Abstract: The present invention provides a circuit board structure with an embedded semiconductor chip and a method for fabricating the same. The circuit board structure includes a carrier board having a first surface, a second surface, and a through hole penetrating the carrier board from the first surface to the second surface; a semiconductor chip having an active surface whereon a plurality of electrode pads are formed and a non-active surface, embedded in the through hole; a photosensitive first dielectric layer formed on the first surface of the carrier board and an opening formed thereon to expose the non-active surface of the semiconductor chip; a photosensitive second dielectric layer formed on the second surface of the carrier board and the active surface of the semiconductor chip.

Abstract: A carrier structure for a semiconductor chip and a method for manufacturing the same are disclosed. The method includes the following steps: providing a carrier board having at least one through cavity, wherein a removable film is formed on the surface of the carrier board, and a semiconductor chip is temporarily fixed in the through cavity by the removable film; filling the gap between the through cavity of the carrier board and the semiconductor chip with an adhesive material in order to fix the semiconductor chip; and removing the removable film. The disclosed method can reduce the alignment error resulted from the tiny shift of the semiconductor chip caused by jitters before the semiconductor is fixed in the cavity, thereby to increase the accuracy of the alignment, to facilitate fine wiring, and to meet the trend toward compact size of semiconductor packages.

Abstract: A circuit board with identifiable information and a method for fabricating the same are proposed. At least one insulating layer within the circuit board has a non-circuit area free of a circuit layout. A plurality of openings are formed in the non-circuit area of the insulating layer. A patterned circuit layer is formed on the insulating layer. Metal identifiable information is disposed in the openings of the non-circuit area. By this arrangement, a product status of the circuit board can be traced and identified via the metal patterned information.

Abstract: The present invention provides a circuit board structure and a method of fabricating circuit board structure the same, the circuit board structure consisting of a carrier board having a first surface and an opposed second surface, the carrier board being formed with at least one through hole penetrating the first and second surfaces; a conductive pillar formed in the through hole by electroplating; and a first circuit layer and a second circuit layer respectively formed on the first and second surfaces of the carrier board, the first and second circuit layers being electrically connected to the two end portions of the conductive pillar, thereby reducing spacing between adjacent conductive pillars of the carrier board and achieving high density circuit layout.

Abstract: A substrate with surface finished structure and a method for manufacturing the same are disclosed. The method comprises: forming a circuit layer and a solder mask on the surface of the substrate in sequence, wherein a plurality of openings are formed in the solder mask to expose the portion of the circuit layer to be electrical contact pads which having at least a wire bonding pad and a plurality of solder pads; and forming a Ni/Au layer on the surface of the wire bonding pad and a chemical gold layer on the surface of the solder pads. Therefore, the disclosed structure can prevent the electrical contact pads from oxidation for a long time.

Abstract: The present invention provides a circuit board structure, the circuit board structure consisting of a carrier board having a first surface and an opposed second surface, the carrier board being formed with at least one through hole penetrating the first and second surfaces; a conductive pillar formed in the through hole by electroplating; and a first circuit layer and a second circuit layer respectively formed on the first and second surfaces of the carrier board, the first and second circuit layers being electrically connected to the two end portions of the conductive pillar, thereby reducing spacing between adjacent conductive pillars of the carrier board and achieving high density circuit layout.

Abstract: A semiconductor device integrated with optoelectronic components includes a carrier board with at least two openings; a first and a second optoelectronic component disposed in the openings respectively, each of them having an active surface and an opposite non-active surface, wherein the active surface has a plurality of electrode pads and an optical active area; a dielectric layer formed on a surface of the carrier board and the active surfaces, and having a plurality of vias and openings to expose the electrode pads and the optical active areas respectively; and a circuit layer formed on a surface of the dielectric layer and electrically connected to the electrode pads directly.

Abstract: A thin circuit board includes a dielectric layer with at least one cavity formed on a surface thereof; a metal pad formed in the cavity; at least one circuit layer formed on another surface of the dielectric layer; and a plurality of conductive vias formed in the dielectric layer to electrically connect the circuit layer to the metal pad. A build-up circuit structure is formed on the surface of the dielectric layer where the circuit layer is formed, and a conductive element is formed on a surface of the metal pad, so as to form a single-sided build-up circuit structure that prevents the use of a core board. Therefore, the thickness of the circuit board can be reduced and the impedance of the circuit board can also be reduced due to elimination of the use of plated through holes.

Abstract: A method for fabricating a circuit board having a conductive structure is disclosed. The method includes: forming first and second insulating protective layers respectively on first and second surfaces of a circuit board; forming a conductive layer on the first insulating protective layer and the openings; forming first and second resist layers on the conductive layer and the second insulating protective layer respectively; forming first electrically connecting structures by electroplating on the exposed conductive layer over a plurality of first and second electrically connecting pads in openings of the first resist layer; removing the first and the second resist layers and the conductive layer covered by the first resist layer; and forming second electrically connecting structures by stencil printing on the conductive layer over the second electrically connecting pads on the first surface and on a plurality of third electrically connecting pads of the second surface of the circuit board.

Abstract: The present invention relates to a method to fabricate a flip chip substrate structure, which comprises: providing a carrier; forming a patterned resist layer on the surface of the carrier; forming sequentially a first metal layer, an etching-stop layer, and a second metal layer; removing the resist layer, forming a patterned first solder mask, and then forming at least one first circuit build up structure thereon; forming additionally a patterned second solder mask on the circuit build up structure; respectively removing the carrier, the first metal layer, and the etching-stop layer; and forming solder bumps on both sides of the circuit build up structure. The method increases integration and achieves the purpose of miniaturization. The method solves the problem of circuit layer multiplicity and process complexity.

Abstract: A circuit board structure having an embedded semiconductor chip and a method for fabricating the same are disclosed. The circuit board structure includes: a carrier board formed with at least one through hole; a semiconductor chip received in the through hole of the carrier board, the semiconductor chip having an active surface and a non-active surface, wherein the active surface is provided with a plurality of electrode pads; a dielectric layer formed on surfaces of the carrier board and the semiconductor chip and formed with a plurality of openings for exposing the electrode pads of the semiconductor chip; and a composite circuit layer formed on the dielectric layer, including a thinned metal layer, conductive layer, and electroplated metal layer, and electrically connected to the electrode pads by conductive structures formed in the openings of the dielectric layer.

Abstract: A flip chip substrate structure and a method to fabricate thereof are disclosed. The structure comprises a build up structure, a first solder mask and a second solder mask. Plural first and second electrical contact pads are formed on the first and second surface of the build up structure, respectively. A first solder mask having plural openings is formed on the first surface of the build up structure, and the openings expose the first electrical contact pads, wherein the aperture of the openings of the first solder mask are equal to the outer diameter of the first electrical contact pads. A second solder mask having plural openings is formed on the second surface of the build up structure, and the openings expose the second electrical contact pads, wherein the aperture of the openings of the second solder mask are smaller than the outer diameter of the second electrical contact pads.

Abstract: A method for fabricating conductive bumps of a circuit board is proposed. First of all, a circuit board having a first surface and a corresponding second surface is provided. A circuit structure having a plurality of conductive pads is formed on each of the first surface and the second surface, and conductive structures are formed in the circuit board for electrically connecting the circuit structures. Also, an insulating layer having a plurality of openings penetrating therethrough is formed on the circuit board for exposing the conductive pad. Then, a conductive layer is formed on a surface of the insulating layer having the opening formed on the first surface of the circuit board. An electroplating process is performed via the conductive layer and the conductive structure, such that a conductive bump is formed on the conductive pad located on the second surface of the circuit board.