Abstract: A stack structure of circuit boards embedded with semiconductor components therein is proposed, which includes at least two semiconductor components embedded circuit boards, a plurality of conductive bumps, and at least one adhesive layer. The circuit boards are each formed with a circuit layer having a plurality of electrical connection pads. The conductive bumps are formed on the electrical connection pads of at least one of the circuit boards. The adhesive layer is formed between the circuit boards such that a portion of the adhesive layer between the conductive bumps and the electrical connection pads, or between the opposing conductive bumps, forms a conductive channel and thereby forms an electrical connection between the circuit boards.

Abstract: A method for repairing an electrical circuit of a circuit board is proposed. The method includes providing a circuit board having a patterned circuit layer, wherein the patterned circuit layer includes an electrical circuit having at least one defect formed therein; and providing a microelectrode for performing a micro-electroplating process at a position corresponding to the defect of the electrical circuit to form a circuit material, so as to repair the electrical circuit of the circuit board. Alternatively, the micro-electroplating process may be replaced with a micro-deposition process by using a micro-droplet to form the circuit material at the aforementioned position.

Abstract: A circuit board structure of integrated optoelectronic components is composed of: a carrying board with at least one through opening; a first optoelectronic component accommodated in the through opening, which has an active surface and a non-active surface. A dielectric layer, a circuit layer and build-up layers are successively formed on the active surface of the optoelectronic component and the carrying board. A first opening penetrates the dielectric layer and the circuit layer while a second opening penetrates the build-up layers. The present invention provides that the circuit layer is directly formed on the surface of the first optoelectronic component so that the registration between the circuit layer and the electrode pads of the optoelectronic component is improved. Moreover, the optical transmission component for transmitting signal is integrated in the build-up circuit layer. Thus, the cost is reduced, the production is improved and the volume is shrunken.

Abstract: A method of manufacturing a coreless packaging substrate is disclosed. The method can produce a coreless packaging substrate which comprises: at least a built-up structure having a first solder mask and a second solder mask, wherein a plurality of openings are formed in the first and second solder mask to expose the conductive pads of the built-up structure; and a plurality of solder bumps as well as solder layers formed on the conductive pads. Therefore, the invention can produce the coreless packaging substrate with high density of circuit layout, less manufacturing steps, and small size.

Abstract: A method for manufacturing a coreless packaging substrate is disclosed. The method can produce a coreless packaging substrate which comprises: at least a built-up structure having a first solder mask and a second solder mask, wherein a plurality of openings are formed in the first and second solder mask to expose the conductive pads of the built-up structure; and a plurality of solder bumps as well as solder layers formed on the conductive pads. Therefore, the invention can produce the coreless packaging substrate with high density of circuit layout, less manufacturing steps, and small size.

Abstract: A method of manufacturing a coreless package substrate together with a conductive structure of the substrate is disclosed. The method can produce a coreless package substrate which comprises: at least a built-up structure having a first solder mask and a second solder mask, wherein a plurality of openings are formed in the first and second solder mask to expose the conductive pads of the built-up structure; and a plurality of solder bumps as well as solder layers formed on the conductive pads. Therefore, the invention can produce the coreless package substrate with high density of circuit layout, less manufacturing steps, and small size.

Abstract: A carrier board structure with a semiconductor chip embedded therein and a method for fabricating the same are proposed. A rectangular cavity is formed at a predetermined position of the carrier board, and at least a breach is formed at a corner of the rectangular cavity, wherein the breach is composed of a plurality of drilling holes. Thus, the breach is capable of providing the rectangular cavity with a larger space for receiving a semiconductor chip in the rectangular cavity, when in the process of disposing the semiconductor chip into the rectangular cavity.

Abstract: A carrying structure of electronic components is proposed. The carrying structure includes at least one supporting board with at least one cavity disposed thereon, at least one adhesive layer formed on the supporting board, and at least one electronic component having an active face and a non-active face located in the cavity. The gap between the cavity and the electronic component is filled with a portion of the adhesive layer, and thus the electronic component is fixed in the cavity of the supporting board.

Abstract: A method of embedding a semiconductor chip in a support plate and an embedded structure thereof are proposed. A first dielectric layer having a reinforced filling material is provided, and a semiconductor chip is mounted on the first dielectric layer. A support plate having an opening and a second dielectric layer having a reinforced filling material are provided. The first dielectric layer mounted with the semiconductor chip, the support plate, and the second dielectric layer are pressed together, such that the semiconductor chip is received in the opening of the support plate, and the dielectric layers fill in a gap between the semiconductor chip and the opening of the support plate. The reinforced filling material of the dielectric layers can maintain flatness and consistency of the semiconductor chip embedded in the support plate, and fine circuits can be fabricated on the support plate by build-up and electroplating processes.

Abstract: This invention discloses a method for electroplating nickel/gold on electrically connecting pads on a substrate for chip package and structure thereof. The method comprises: forming a conductive film on a substrate circuit-patterned and defined with a circuit layer; forming on the substrate a resist with an opening for exposing a portion of the conductive film in an electrically connecting pad area intended for the circuit layer; removing a portion of the conductive film not covered with the resist; forming another resist on the substrate to cover a portion of the conductive film residually exposing from the resist; electroplating nickel/gold on at least one electrically connecting pad on the substrate such that the electrically connecting pad is electroplated with a nickel/gold layer; removing the resists and the conductive film thereunder; and forming a solder mask on the substrate, wherein the electrically connecting pad electroplated with the nickel/gold layer is exposed from the solder mask.

Abstract: An embedded chip package structure is proposed. The embedded chip package structure includes a supporting board with a protruding section, a semiconductor chip formed on the protruding section of the supporting board, a dielectric layer formed on the supporting board and the semiconductor chip, and a circuit layer formed on the dielectric layer. The circuit layer is electrically connected to electrode pads of the semiconductor chip via a plurality of conducting structures formed inside the dielectric layer such that the semiconductor chip can be electrically connected to an external element through the circuit layer. By varying the thicknesses of the protruding section, the dielectric layer and the supporting board, warpage of the package structure resulted from temperature change during the fabrication process can be prevented.

Abstract: A method for fabricating a circuit board having a conductive structure is disclosed. The method includes: forming first and second insulating protective layers respectively on first and second surfaces of a circuit board; forming a conductive layer on the first insulating protective layer and the openings; forming first and second resist layers on the conductive layer and the second insulating protective layer respectively; forming first electrically connecting structures by electroplating on the exposed conductive layer over a plurality of first and second electrically connecting pads in openings of the first resist layer; removing the first and the second resist layers and the conductive layer covered by the first resist layer; and forming second electrically connecting structures by stencil printing on the conductive layer over the second electrically connecting pads on the first surface and on a plurality of third electrically connecting pads of the second surface of the circuit board.

Abstract: A circuit board and a fabrication method thereof. Providing the insulating layer with a first conductive layer formed thereon; wherein the insulating layer was formed on a core substrate with at least one patterned circuit layer thereon. A first resist layer is applied on a first conductive layer, forming first openings to expose the first conductive layer. A first patterned circuit layer, including conductive pads and traces, is formed in the first openings. A second resist layer is applied to cover the traces, and a conductive post is formed on each conductive pad. The first and second resist layers and the first conductive layer underneath the first resist layer are removed. A dielectric material layer is formed on the insulating layer with first patterned circuit layer, forming second openings to expose the conductive posts. A second conductive layer is formed on the dielectric material layer and in the second openings.

Abstract: An embedded capacitor structure in a circuit board and a method for fabricating the same are proposed. The circuit board is formed with a first circuit layer on at least one surface thereof, wherein the first circuit layer has at least one first electrode plate for the capacitor structure. Then, a dielectric layer is formed on the first circuit layer and made flush with the first circuit layer. The dielectric layer has a relatively low dielectric constant and good fluidity to effectively fill the spaces between patterned traces of the first circuit later. A capacitive material is deposited on the dielectric layer and the first circuit layer. Finally, a second circuit layer is formed on the capacitive material and has at least one second electrode plate corresponding to the first electrode plate, together with the capacitive material disposed in-between, to form the capacitor structure.

Abstract: A method for fabricating a circuit board with a conductive structure and the same are proposed. A buffer metal layer is formed on an electrically connecting pad of a circuit layer of a circuit board in advance. A conductive structure is then formed on the buffer metal layer to form the conductive structure of the present invention and is connected to the circuits located in the different layers of the circuit board. The combining strength of the conductive structure and the electrically connecting pad is reinforced by the buffer metal layer as the buffer metal layer has high ductility. The long-term electrical quality and stability are also enhanced.

Abstract: A circuit board device with a fine conductive structure is proposed. A circuit board having at least a circuit layer is provided and the circuit layer has at least one electrically conductive pad. At least one first dielectric layer is formed on surfaces of the circuit board and the circuit layer and has at least one opening to expose the electrically conductive pad of the circuit layer. At least a first fine conductive structure made of conductive material with high ductility is formed in the opening of the first dielectric layer and is electrically connected to the electrically conductive pad of the circuit layer. The top surface of the first fine conductive structure is higher than, level with or lower than the surface of the first dielectric layer. Moreover, a conductive pad may be further formed on the top surface of the first fine conductive structure.

Abstract: Conductive structures for electrically conductive pads of a circuit board and fabrication method thereof are proposed.

Abstract: A substrate assembly with direct electrical connection as a semiconductor package is disclosed, which includes a carrier structure formed with at least a cavity; at least a semiconductor chip received in the cavity of the carrier structure having a plurality of electrically connecting pads formed thereon; at least a build-up circuit structure formed on the semiconductor chip and the carrier structure, wherein the build-up circuit structure has conductive structures for electrically connecting to the electrically connecting pads of the semiconductor chip; and a heat sink partially attached to the carrier structure for sealing the cavity. In that the heat sink directly contacts the semiconductor chip, heat generated during operation of the chip can be effectively dissipated, and more mounting space is provided for mounting electronic components, enhancing the electrical property thereof.

Abstract: A circuit board structure with embedded selectable passive components and a method for fabricating the same are proposed, wherein a plurality of passive components are embedded in a circuit board and a plurality of electrical connections are formed on a surface of the circuit board and electrically connected to the passive components. A circuit structure is formed close to the electrical connections for selectively forming a conductive layer thereon to electrically connect a portion of the passive components according to different electrical situations, in order to provide a set of passive components for electrical design of electronic devices.

Abstract: A circuit board structure having a capacitor array and an embedded electronic component and a method for fabricating the same are proposed. Two carrier boards and a high dielectric constant material layer are provided, wherein the carrier boards have electronic components embedded therein and one surface of each carrier board has a plurality of electrode plates. The two carrier boards are laminated with the dielectric constant material layer interposed between them. The electrode plates on the surfaces of the carrier boards are opposite to each other across the high dielectric constant material layer to constitute a capacitor array. Therefore, the capacitor assembly for design of electronic devices is provided.