Abstract: A non-volatile memory structure including a substrate, at least one memory cell, a first doped region, a second doped region, and a third doped region is provided. The memory cell is disposed on the substrate and has a channel region located in the substrate. The first doped region, the second doped region, and the third doped region are sequentially disposed in the substrate in an arrangement direction toward the channel region, and the first doped region is farthest from the channel region. The first doped region and the third doped region are of a first conductive type, and the second doped region is of a second conductive type.

Abstract: A reconfiguring image brightness (RIB) module includes a switch, a first lens, a digital micro-mirror device (DMD), a second lens and a third lens. The switch selectively allows a first image having a light intensity distribution to pass, wherein the first image is formed after an illumination beam passes through a photomask. The first lens outputs a second image by modulating the size of the first image passes through the first lens, and the second image is imaged on the DMD. A third image having a reconfigured light intensity distribution is formed by the DMD, and the third image is outputted to the second lens by the DMD. A fourth image is formed after the third image passes through the second lens, a fifth image is formed after the fourth image passes through the third lens and the fifth image is outputted from the RIB module.

Abstract: The power control circuit of the disclosure is configured for a logic circuit performing a predetermined logic calculation on a plurality of input signals from a memory part and outputting a plurality of output signals after logic calculation. The power control circuit includes a switch part that switches between whether to supply a power voltage to the logic circuit or not; a plurality of detector circuits that respectively detect change of signal level of the input signals, wherein when the change of signal level is detected, detect signals are output respectively; and a control circuit that controls the switch part to supply power voltage to the logic circuit based on at least one detect signal from the detector circuits, wherein on the other hand, when the detect signal is not output from the detector circuits, controls the switch part not to supply power voltage to the logic circuit.

Abstract: The invention provides a manufacturing method of a metal-insulator-metal device, including: forming a first metal layer, an insulation layer, and a second metal layer sequentially on a base to form a metal-insulator-metal structure; forming a patterned mask layer on at least a portion of the second metal layer, etching the second metal layer and the insulation layer on which the patterned mask layer is not formed using an etchant without carbon; and cleaning the etched metal-insulator-metal structure using a mixed solution containing oxidants and metal oxide etchants to remove excess polymer remaining on the metal-insulator-metal structure.

Abstract: A photomask is provided. The photomask includes a substrate, a light-blocking main feature, and sub-resolution assist features (SRAFs). The light-blocking main feature is disposed on the substrate. The SRAFs are disposed on the substrate and located on at least one side of the light-blocking main feature. A space between two adjacent SRAFs of the SRAFs is equal to a width of each of the SRAFs, and a light transmittance of the SRAFs is 100%.

Abstract: A voltage regulation device includes a first transistor, a first bias current source, a bias resistor, a second transistor, a second bias current source, and a detection adjustment circuit. The first transistor is coupled to the first bias current source for outputting a reference voltage. The bias resistor is coupled to the first transistor for receiving a regulation current. The second transistor has a first terminal for receiving a system voltage, a second terminal for outputting an output voltage, and a control terminal for receiving the reference voltage. The second bias current source is coupled to the second terminal of the second transistor. The detection adjustment circuit is coupled to the first transistor and the second transistor. When the output voltage is too low, the detection adjustment circuit activates the compensation current source to increase the voltage at the control terminal of the second transistor.

Abstract: A nonparametric method for measuring a clustered level of time rank in binary data is provided. A sample set of engineering data is classified into a target group and a reference group, and a rank is set to each sample in a chronological order. A minimum rank and a maximum rank are obtained from the target group, by which a characteristic period is defined. In the characteristic period, an average rank values of the target group and an average rank value of the reference group are calculated. After creating a dummy sample set, the dummy sample set is incorporated into an analysis data set and a new rank is set based on a comparison result of the average rank value of the target group and the average rank value of the reference group, and the minimum rank and the maximum rank of the characteristic period to obtain adjusted test data. A Mann-Whitney U test is executed on the adjusted test data to obtain a clustered level index of time rank in binary data.

Abstract: A nonparametric method for measuring a clustered level of time rank in binary data is provided. A sample set of engineering data is classified into a target group and a reference group, and a rank is set to each sample in a chronological order. A minimum rank and a maximum rank are obtained from the target group, by which a characteristic period is defined. In the characteristic period, an average rank values of the target group and an average rank value of the reference group are calculated. After creating a dummy sample set, the dummy sample set is incorporated into an analysis data set and a new rank is set based on a comparison result of the average rank value of the target group and the average rank value of the reference group, and the minimum rank and the maximum rank of the characteristic period to obtain adjusted test data. A Mann-Whitney U test is executed on the adjusted test data to obtain a clustered level index of time rank in binary data.

Abstract: An image sensor includes a semiconductor substrate with at least one recess disposed on its surface and in the photosensitive area defined on the surface of the semiconductor substrate, a first-conductivity-type doped region disposed in the semiconductor substrate and in the photosensitive area, and a second-conductivity-type doped region disposed on the surface of the first-conductivity-type doped region and on the surface of the recess. A photosensitive device of the image sensor is formed of the first-conductivity-type doped region and the second-conductivity-type doped region.

Abstract: A process control method is provided for performing a deposition process on a plurality of wafers of a batch. The process control method includes: deciding a placement location of the wafers of the batch according to the history information of a tool and the product information of the batch; calculating a target value of each placement location according to the placement location of the wafers of the batch and the history information of the tool; calculating a process parameter according to the history information of the tool, the product information of the batch, and the target value of each placement location; and performing a deposition process according to the placement location of the wafers of the batch and the process parameter.

Abstract: A semiconductor memory apparatus performs a selection in a normal readout/write-in mode and an automatic refreshing mode and includes a sense amplifier reading out data from a memory device, a first switching device connecting a first power supply voltage acting as an overdrive voltage to a first power supply intermediate node during a first period and then connecting a second power supply voltage acting as an array voltage to the first power supply intermediate node, a second switching device connecting the fourth power supply voltage to a second power supply intermediate node of the sense amplifier when the sense amplifier is driven, a first capacitor connected to the overdrive voltage and charging it, a third switching device switched on in the automatic refreshing mode, and a voltage generator generating a third power supply voltage and applying it and the first power supply voltage in parallel through the third switching device.

Abstract: A bio-sensor includes a substrate having a light-sensing region thereon. A first dielectric layer, a diffusion barrier layer, and a second dielectric layer are disposed on the substrate. A trenched recess structure is formed in the second dielectric layer, which is filled with a light filter layer that is capped with a cap layer. A first passivation layer and a nanocavity construction layer are disposed on the cap layer. A nanocavity is formed in the nanocavity construction layer. The sidewall and bottom surface of the nanocavity is lined with a second passivation layer.

Abstract: A method, image processing system, and computer-readable recording medium for item defect inspection are provided. The method is as follows. A test image and a reference image of a test item are received. A test block and a corresponding reference block are obtained from the test image and the reference image to generate a test block image and a reference block image. The test block image and the reference block image are respectively partitioned into multiple sub-blocks. All interfering sub-blocks are identified and filtered out from the test block image and the reference block image, and a shift calibration parameter is obtained accordingly. The test block in the test image is calibrated based on the shift calibration parameter to generate a calibrated test block image. The calibrated test block image and the reference block image are compared to obtain defect information of the test item corresponding to the test block.

Abstract: The semiconductor memory device selectively switches at least two banks based on an input parallel address for writing or reading data, and includes a control unit, which controlled according to a following method: in a first data access, the semiconductor memory device is accessed according to the input parallel address; and then in a second data access and after, the semiconductor memory device is accessed according to a serial address different to the parallel address. Moreover, the semiconductor memory device is constructed by respectively connecting memory cells to intersections of word lines and bit lines, and the serial address contains: a 1st serial address for selecting one word line in the word lines, and a 2nd serial address for selecting one bit line in the bit lines.

Abstract: A multi-layer, crown-shaped MIM capacitor includes a base having therein conductive region, an inter-metal dielectric (IMD) layer on the base, a capacitor trench penetrating through the IMD layer and exposing the conductive region, a capacitor lower electrode structure including a first electrode and a second electrode surrounded by the first electrode, a conductive supporting pedestal within the capacitor trench for fixing and electrically connecting the bottom portions of the first and second electrodes, a capacitor dielectric layer conformally lining the first and second electrodes and a top surface of the conductive supporting pedestal, and a capacitor upper electrode on the capacitor dielectric layer.

Abstract: A latch circuit provided herein includes an input circuit including a PMOS transistor that is configured for input and enables a signal current to flow into the PMOS transistor; a first inverter comprising a first PMOS transistor, a first NMOS transistor, and a first node; a second inverter comprising a second PMOS transistor, a second NMOS transistor, and a second node. The signal current corresponds to a sense voltage from a sense amplifier. The first PMOS transistor and the first NMOS transistor are connected to each other through the first node, and the first node is connected to the input circuit. The second PMOS transistor and the second NMOS transistor are connected to each other through the second node. The first inverter and the second inverter are cascaded.

Abstract: A dispatch control method for a furnace process including the following steps is provided. Before a plurality of lots of wafers is loaded into a furnace, the characteristic variation value of each of the plurality of lots of wafers is calculated. The plurality of lots of wafers is ordered according to the size of the characteristic variation values. The plurality of lots of wafers is placed in the furnace in a descending order of the characteristic variation values corresponding to a plurality of locations in the furnace causing the characteristic variation values to change from smaller to larger.

Abstract: A non-volatile semiconductor memory device comprising a control circuit is provided, the control circuit performing a data erasure by applying predetermined erase voltages to predetermined blocks of a memory cell array including memory cells disposed on each intersection of a plurality of word lines and a plurality of bit lines, and the control circuit applying the erase voltages to the memory cells to erase data by applying word line voltages different to each other to even-numbered word lines and odd-numbered word lines of the memory cell array except to an edge part thereof, and by applying a voltage different to the word line voltages to the word line in the edge part of the memory cell array.

Abstract: A bio-sensor includes a substrate having a light-sensing region thereon. A first dielectric layer, a diffusion barrier layer, and a second dielectric layer are disposed on the substrate. A trenched recess structure is formed in the second dielectric layer, which is filled with a light filter layer that is capped with a cap layer. A first passivation layer and a nanocavity construction layer are disposed on the cap layer. A nanocavity is formed in the nanocavity construction layer. The sidewall and bottom surface of the nanocavity is lined with a second passivation layer.

Abstract: A semiconductor device including a substrate, at least one sensor, a dielectric layer, at least one light pipe structure, at least one pad, a shielding layer, and a protection layer is provided. The sensor is located in the substrate of a first region. The dielectric layer is located on the substrate. The light pipe structure is located in the dielectric layer of the first region. The light pipe structure corresponds to the sensor. The pad is located in the dielectric layer of a second region. The shielding layer is located on the dielectric layer, wherein the light pipe structure is surrounded by the shielding layer. The protection layer is located on the shielding layer. At least one pad opening is disposed in the dielectric layer, the shielding layer, and the protection layer above the pad. The pad opening exposes a top surface of the corresponding pad.