Patents Assigned to Powerchip Technology Corporation
-
Publication number: 20120181606Abstract: A vertical channel transistor array includes a plurality of embedded bit lines, a plurality of bit line contacts, a plurality of embedded word lines, and a current leakage isolation structure. An active area of a vertical channel transistor is defined by the semiconductor pillars. The embedded bit lines are disposed in parallel in a semiconductor substrate and extended in a column direction. Each of the bit line contacts is respectively disposed at a side of one of the embedded bit lines. The embedded word lines are disposed in parallel above the embedded bit lines and extended in a row direction. Besides, the embedded word lines and the semiconductor pillars in the same row are connected but spaced by a gate dielectric layer. The current leakage isolation structure is disposed at ends of the embedded bit lines to prevent current leakage between the adjacent bit line contacts.Type: ApplicationFiled: January 18, 2011Publication date: July 19, 2012Applicant: Powerchip Technology CorporationInventor: Yukihiro Nagai
-
Patent number: 8223541Abstract: A non-volatile semiconductor memory and a writing method thereof are provided for preventing miswriting induced by gate-induced-drain leakage (GIDL). The non-volatile semiconductor memory comprises a non-volatile memory cell array 10 for recording multiple values by setting a plurality of different thresholds to each memory cell transistor that is connected in series between selection transistors Qs1 and Qs2 on two terminals of a selected bit line; and a control circuit 11 for controlling writing of the data from the memory cell array 10. The control circuit 11 records two values for at least a plurality of first memory cell transistors Q0, Q1, Q32 and Q33 respectively adjacent to the selection transistors Qs1 and Qs2 on two terminals of the bit line, and records more than three values for a plurality of second transistors Q2˜Q31 other than the first memory cell transistors.Type: GrantFiled: December 3, 2009Date of Patent: July 17, 2012Assignee: Powerchip Technology CorporationInventor: Riichiro Shirota
-
Patent number: 8219242Abstract: An automated material handling system for combining over-head conveyer with a material control system is disclosed. First and second virtual stocker codes are respectively assigned to first and second virtual stocker of an over-head conveyer (OHC) using a material control system. A front opening unified pod (FOUP) is moved to and loaded in the first virtual stocker using a transport system controller. The FOUP is loaded in a track of the OHC and assigned a virtual vehicle code. The FOUP is moved, along the track, to the second virtual stocker and loaded in the second virtual stocker, while the virtual vehicle code is being removed, and is removed therefrom using the transport system controller.Type: GrantFiled: July 2, 2009Date of Patent: July 10, 2012Assignee: Powerchip Technology CorporationInventors: Chia-Cheng Kuo, Yuan-Chung Cheng
-
Publication number: 20120161221Abstract: A non-volatile memory having a tunneling dielectric layer, a floating gate, a control gate, an inter-gate dielectric layer and a first doping region and a second doping region is provided. The tunneling dielectric layer is disposed on a substrate. The floating gate is disposed on the tunneling dielectric layer, and has a protruding portion. The control gate is disposed over the floating gate to cover and surround the protruding portion. The protruding portion of the floating gate is fully covered and surrounded by the control gate in any direction, including extending directions of bit lines, word lines and an included angle formed between the word line and the bit line. The inter-gate dielectric layer is disposed between the floating gate and the control gate. The first doping region and the second doping region are respectively disposed in the substrate at two sides of the control gate.Type: ApplicationFiled: February 22, 2011Publication date: June 28, 2012Applicant: POWERCHIP TECHNOLOGY CORPORATIONInventors: Ya-Jui Lee, Ying-Chia Lin
-
Publication number: 20120153371Abstract: A dynamic random access memory cell having vertical channel transistor includes a semiconductor pillar, a drain layer, an assisted gate, a control gate, a source layer, and a capacitor. The vertical channel transistor has an active region formed by the semiconductor pillar. The drain layer is formed at the bottom of the semiconductor pillar. The assisted gate is formed beside the drain layer, and separated from the drain layer by a first gate dielectric layer. The control gate is formed beside the semiconductor pillar, and separated from the active region by a second gate dielectric layer. The source layer is formed at the top of the semiconductor pillar. The capacitor is formed to electrical connect to the source layer.Type: ApplicationFiled: February 17, 2011Publication date: June 21, 2012Applicant: POWERCHIP TECHNOLOGY CORPORATIONInventors: Hui-Huang Chen, Chih-Yuan Chen, Sheng-Fu Yang, Chun-Cheng Chen
-
Publication number: 20120103434Abstract: A system for managing liquid supply suitable for a process equipment with a liquid tank is disclosed. The system includes a host, a data-reading tool, a system controller and a tank-locking device. The host stores a built-in liquid database. The data-reading tool used for reading data related to the liquid tank is electrically connected to the host. The host receives the data related to the liquid tank from the data-reading tool, and the received data mapped with the liquid database. The system controller drives the tank-locking device according to the signal from the host to whether or not allow replacement of the liquid tank.Type: ApplicationFiled: January 9, 2012Publication date: May 3, 2012Applicant: POWERCHIP TECHNOLOGY CORPORATIONInventors: Yen-Liang Chen, Yuh-Shyang Su, Sou-Yung Hsieh
-
Publication number: 20120104088Abstract: A system for managing liquid supply suitable for a process equipment with a liquid tank is disclosed. The system includes a host, a data-reading tool, a system controller and a tank-locking device. The host stores a built-in liquid database. The data-reading tool used for reading data related to the liquid tank is electrically connected to the host. The host receives the data related to the liquid tank from the data-reading tool, and the received data mapped with the liquid database. The system controller drives the tank-locking device according to the signal from the host to whether or not allow replacement of the liquid tank.Type: ApplicationFiled: January 9, 2012Publication date: May 3, 2012Applicant: POWERCHIP TECHNOLOGY CORPORATIONInventors: Yen-Liang Chen, Yuh-Shyang Su, Sou-Yung Hsieh
-
Publication number: 20120092925Abstract: A vertical capacitor-less DRAM cell is described, including: a source layer having a first conductivity type, a storage layer disposed on the source layer and having a second conductivity type, an active layer disposed on the storage layer and having the first conductivity type, a drain layer disposed on the active layer and having the second conductivity type, an address gate disposed beside the active layer and separated from the same by a first gate dielectric layer, and a storage gate disposed beside the storage layer and separated from the same by a second gate dielectric layer. The DRAM cell can be written by turning on the MOSFET formed by the storage layer, the active layer, the drain layer, the first gate dielectric layer and the address gate to inject carriers into the storage layer from the active layer.Type: ApplicationFiled: October 15, 2010Publication date: April 19, 2012Applicant: POWERCHIP TECHNOLOGY CORPORATIONInventors: Hui-Huang Chen, Chih-Yuan Chen, Chun-Cheng Chen, Ching-Ching Tsai, Ting-Jyun He, Tai-Liang Hsiung
-
Patent number: 8140184Abstract: A system for managing liquid supply suitable for a process equipment with a liquid tank is disclosed. The system includes a host, a data-reading tool, a system controller and a tank-locking device. The host stores a built-in liquid database. The data-reading tool used for reading data related to the liquid tank is electrically connected to the host. The host receives the data related to the liquid tank from the data-reading tool, and the received data mapped with the liquid database. The system controller drives the tank-locking device according to the signal from the host to whether or not allow replacement of the liquid tank.Type: GrantFiled: January 30, 2008Date of Patent: March 20, 2012Assignee: Powerchip Technology CorporationInventors: Yen-Liang Chen, Yuh-Shyang Su, Sou-Yung Hsieh
-
Patent number: 8131954Abstract: A memory device is provided. The memory device includes a memory array formed by a plurality of multi level cells, a determining circuit and a data reading circuit. The memory array includes a plurality of page units, each including a main data and an auxiliary data corresponding to the main data, wherein the auxiliary data includes a plurality of flag bits. The determining circuit generates a determination bit according to the flag bits. The data reading circuit obtains information corresponding to the main data according to the determination bit.Type: GrantFiled: December 18, 2008Date of Patent: March 6, 2012Assignee: Powerchip Technology CorporationInventors: Chun-Yi Tu, Te-Chang Tseng, Hideki Arakawa, Takeshi Nakayama
-
Publication number: 20120018801Abstract: A vertical channel transistor array has an active region formed by a plurality of semiconductor pillars. A plurality of embedded bit lines are arranged in parallel in a semiconductor substrate and extended along a column direction. A plurality of bit line contacts are respectively disposed on a side of one of the embedded bit lines. A plurality of embedded word lines are arranged in parallel above the embedded bit lines and extended along a row direction. Besides, the embedded word lines connect the semiconductor pillars in the same row with a gate dielectric layer sandwiched between the embedded word lines and the semiconductor pillars. The current leakage isolation structure is disposed at terminals of the embedded bit lines to prevent current leakage between the adjacent bit line contacts.Type: ApplicationFiled: July 20, 2010Publication date: January 26, 2012Applicant: POWERCHIP TECHNOLOGY CORPORATIONInventors: Heiji Kobayashi, Yukihiro Nagai
-
Publication number: 20120015494Abstract: A method for manufacturing a capacitor bottom electrode of a dynamic random access memory is provided. The method comprises providing a substrate having a memory cell region and forming a polysilicon template layer on the memory cell region of the substrate. A supporting layer is formed on the polysilicon template layer and plural openings penetrating through the supporting layer and the polysilicon template layer are formed and a liner layer is formed on at least a portion of the polysilicon template layer exposed by the openings A conductive layer substantially conformal to the substrate is formed on the substrate. A portion of the conductive layer on the supporting layer is removed so as to form plural capacitor bottom electrodes. Using the polysilicon template layer, the openings with relatively better profiles are formed and the dimension of the device can be decreased.Type: ApplicationFiled: July 15, 2010Publication date: January 19, 2012Applicant: POWERCHIP TECHNOLOGY CORPORATIONInventors: Heiji Kobayashi, Yukihiro Nagai
-
Patent number: 8081522Abstract: Within a page buffer 14 which is coupled to a non-volatile memory cell array 10 and temporally stores data as the data with a predetermined page unit is written in and read out to/from the memory cell array 10, at least one latch circuit 14v-1 including a bit line selector 14s, a page buffer unit circuit 14u including two latch L1, L2, and a latch L3 is set up for a plurality of bit lines. The bit line selector 14s selects one bit line and couples it to the page buffer unit circuit 14u. The latch L1 temporally stores the data which are read out from the memory cell of the selected bit line, and then outputs the data through the latch L2 or L3. On the other hand, the latch L1 temporally stores the programming data inputted through the latch L2 or L3, and after that outputs it to the memory cell of the selected bit line for programming.Type: GrantFiled: November 6, 2009Date of Patent: December 20, 2011Assignee: Powerchip Technology CorporationInventor: Hiroki Murakami
-
Patent number: 8068362Abstract: A non-volatile semiconductor memory device capable of preventing reading failure during the occurrence of the FG-FG coupling effect is disclosed. The non-volatile semiconductor memory device includes a memory cell array, each cell of which stores at least two bits, such as LSB and MSB, using different threshold voltages. In addition, the device includes a control circuit for controlling the data-reading operation of the memory cell array. When the reading operation of the memory cells of a first word line is performed, the memory cells of a second word line adjacent to the first word line are examined to determine whether the writing operation of the MSB is performed. If the writing operation of the MSB is performed, a pre-charge voltage of the bit lines connecting to the memory cells of the first word line is reduced to a predetermined voltage for canceling out the raising of the threshold voltage caused by the coupling effect between gate electrodes.Type: GrantFiled: December 8, 2009Date of Patent: November 29, 2011Assignee: Powerchip Technology CorporationInventor: Tsuyoshi Ota