Patents Assigned to Powertech Technology Inc.
  • Patent number: 10950593
    Abstract: A package structure including a redistribution structure, a die, at least one connecting module, a first insulating encapsulant, a chip stack, and a second insulating encapsulant. The die is disposed on and electrically connected to the redistribution structure. The connecting module is disposed on the redistribution structure. The connecting module has a protection layer and a plurality of conductive bars. The conductive bars are embedded in the protection layer. The protection layer includes a plurality of openings corresponding to the conductive bars. The first insulating encapsulant encapsulates the die and the connecting module. The chip stack is disposed on the first insulating encapsulant and the die. The chip stack is electrically connected to the connecting module. The second insulating encapsulant encapsulates the chip stack.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: March 16, 2021
    Assignee: Powertech Technology Inc.
    Inventors: Shang-Yu Chang Chien, Hung-Hsin Hsu, Nan-Chun Lin
  • Publication number: 20210074661
    Abstract: A semiconductor package structure including a circuit substrate, at least one chip, an encapsulant, a plurality of conductive connectors, a redistribution layer, and a plurality of conductive terminals is provided. The circuit substrate has a first surface and a second surface opposite to the first surface. The at least one chip has an active surface and a rear surface opposite to the active surface. The at least one chip is disposed on the circuit substrate with the rear surface. The encapsulant encapsulates the at least one chip. The plurality of conductive connectors surrounds the at least one chip. The redistribution layer is located on the encapsulant. The plurality of conductive terminals is located on the second surface. The at least one chip is electrically connected to the plurality of conductive terminals via the redistribution layer, the plurality of conductive connectors, and the circuit substrate. A manufacturing method of a semiconductor package structure is also provided.
    Type: Application
    Filed: January 13, 2020
    Publication date: March 11, 2021
    Applicant: Powertech Technology Inc.
    Inventors: Nan-Chun Lin, Hung-Hsin Hsu, Shang-Yu Chang Chien
  • Patent number: 10944165
    Abstract: An integrated antenna package structure including a circuit board, a chip, an encapsulant and an antenna is provided. The chip is disposed on and electrically connected to the circuit board. The encapsulant encapsulates the chip. The encapsulant has a first surface and a second surface, wherein the normal vector of the first surface is different from the normal vector of the second surface. The antenna is disposed on the first surface and the second surface of the encapsulant. A manufacturing method of an integrated antenna package structure is also provided.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: March 9, 2021
    Assignee: Powertech Technology Inc.
    Inventors: Yun-Hsin Yeh, Hung-Hsin Hsu
  • Publication number: 20210050296
    Abstract: A semiconductor package structure including a circuit substrate, a redistribution layer, and at least two dies is provided. The circuit substrate has a first surface and a second surface opposite the first surface. The redistribution layer is located on the first surface. The redistribution layer is electrically connected to the circuit substrate. The spacing of the opposing sidewalls of the redistribution layer is less than the spacing of the opposing sidewalls of the circuit substrate. The redistribution layer is directly in contact with the circuit substrate. At least two dies are disposed on the redistribution layer. Each of the at least two dies has an active surface facing the circuit substrate. One of the at least two dies is electrically connected to the other of the at least two dies by the redistribution layer. A manufacturing method of a semiconductor package structure is also provided.
    Type: Application
    Filed: September 12, 2019
    Publication date: February 18, 2021
    Applicant: Powertech Technology Inc.
    Inventors: Pei-Chun Tsai, Hung-Hsin Hsu, Shang-Yu Chang Chien, Nan-Chun Lin
  • Publication number: 20210050275
    Abstract: A fan-out semiconductor package and packaging method thereof are disclosed. In the packaging method, a photosensitive material is used to encapsulate multiple bare chips and multiple passive devices, so multiple metal pads of each bare chip and multiple metal terminals of each passive device are exposed out of the photosensitive material by a photolithography process. The exposed metal pads and the exposed metal terminals are directly and electrically connected to a redistribution layer. In the packaging method, the bare chips and the passive devices are located on the same side of the redistribution layer and encapsulated by the photosensitive material. In addition, in the packaging method, the bare chips are not processed by a wafer bump process and does not use the thinner passive devices with high cost. Therefore, a height of the fan-out semiconductor package of the present invention is decreased and a manufacturing cost is relatively reduced.
    Type: Application
    Filed: January 13, 2020
    Publication date: February 18, 2021
    Applicant: Powertech Technology Inc.
    Inventors: Shang-Yu CHANG-CHIEN, Hung-Hsin HSU, Nan-Chun LIN
  • Publication number: 20210035898
    Abstract: A package structure and a manufacturing method thereof are provided. The package structure includes a substrate having a first surface and a second surface opposite to each other, a die electrically coupled to the substrate, an encapsulant disposed over the first surface of the substrate to encapsulate the die, at least one first conductive terminal and at least one second conductive terminal. The at least one first conductive terminal and the at least one second conductive terminal are disposed on the second surface of the substrate. The at least one second conductive terminal is electrically connected to the die through the substrate. The at least one first conductive terminal is overlapped with the die in a direction perpendicular to the second surface of the substrate. A first area of the at least one first conductive terminal is larger than a second area of the at least one second conductive terminal.
    Type: Application
    Filed: July 30, 2019
    Publication date: February 4, 2021
    Applicant: Powertech Technology Inc.
    Inventor: Yutaka Kagaya
  • Publication number: 20210035936
    Abstract: A package structure and a method of manufacturing the same are provided. The package structure includes a substrate, a redistribution layer (RDL) structure, a first die, an encapsulant and a plurality of conductive terminals. The RDL structure is disposed on and electrically connected to the substrate. A width of the RDL structure is less than a width of the substrate. The first die is disposed on the substrate and the RDL structure. The first connectors of the first die are electrically connected to the RDL structure. The second connectors of the first die are electrically connected to the substrate. A first pitch of two adjacent first connectors is less than a second pitch of two adjacent second connectors. The encapsulant is on the substrate to encapsulate the RDL structure and the first die. The conductive terminals are electrically connected to the first die through the substrate and the RDL structure.
    Type: Application
    Filed: August 2, 2019
    Publication date: February 4, 2021
    Applicant: Powertech Technology Inc.
    Inventors: Nan-Chun Lin, Hung-Hsin Hsu, Shang-Yu Chang Chien
  • Patent number: 10892250
    Abstract: A stacked package structure has a metal casing, a stacked chipset, an encapsulation and a redistribution layer. The stacked chipset is adhered in the metal casing. The encapsulation is formed in the metal casing to encapsulate the stacked chip set, but a plurality of surfaces of the metal pads are exposed through the encapsulation. The redistribution layer is further formed on the encapsulation and electrically connects to the metal pads of the stacked chipset. Therefore, the stacked package structure includes the metal casing, so an efficiency of heat dissipation and structural strength are increased.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: January 12, 2021
    Assignee: Powertech Technology Inc.
    Inventors: Ming-Chih Chen, Hung-Hsin Hsu, Yuan-Fu Lan, Hsien-Wen Hsu
  • Patent number: 10862202
    Abstract: An integrated antenna package structure including a circuit board, a chip, an encapsulant and an antenna is provided. The chip is disposed on the circuit board and electrically connected to the circuit board. The encapsulant encapsulates the chip. The antenna is embedded in the encapsulant. The antenna has a first outer surface, the encapsulant has a second outer surface, and the first outer surface is substantially coplanar with the second outer surface. A manufacturing method of an integrated antenna package structure is also provided.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: December 8, 2020
    Assignee: Powertech Technology Inc.
    Inventors: Yun-Hsin Yeh, Hung-Hsin Hsu
  • Publication number: 20200381812
    Abstract: An integrated antenna package structure including a circuit board, a chip, an encapsulant and an antenna is provided. The chip is disposed on and electrically connected to the circuit board. The encapsulant encapsulates the chip. The encapsulant has a first surface and a second surface, wherein the normal vector of the first surface is different from the normal vector of the second surface. The antenna is disposed on the first surface and the second surface of the encapsulant. A manufacturing method of an integrated antenna package structure is also provided.
    Type: Application
    Filed: August 29, 2019
    Publication date: December 3, 2020
    Applicant: Powertech Technology Inc.
    Inventors: Yun-Hsin Yeh, Hung-Hsin Hsu
  • Publication number: 20200381811
    Abstract: An integrated antenna package structure including a circuit board, a chip, an encapsulant and an antenna is provided. The chip is disposed on the circuit board and electrically connected to the circuit board. The encapsulant encapsulates the chip. The antenna is embedded in the encapsulant. The antenna has a first outer surface, the encapsulant has a second outer surface, and the first outer surface is substantially coplanar with the second outer surface. A manufacturing method of an integrated antenna package structure is also provided.
    Type: Application
    Filed: July 29, 2019
    Publication date: December 3, 2020
    Applicant: Powertech Technology Inc.
    Inventors: Yun-Hsin Yeh, Hung-Hsin Hsu
  • Publication number: 20200365486
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a semiconductor die, an encapsulant, a redistribution layer, a polymer pattern and a heat dissipation structure. The semiconductor die has conductive pads at its active side, and is laterally encapsulated by the encapsulant. The redistribution layer is disposed at the active side of the semiconductor die, and spans over a front surface of the encapsulant. The redistribution layer is electrically connected with the conductive pads. The polymer pattern is disposed at a back surface of the encapsulant that is facing away from the front surface of the encapsulant. The semiconductor die is surrounded by the polymer pattern. The heat dissipation structure is in contact with a back side of the semiconductor die that is facing away from the active side, and extends onto the polymer pattern.
    Type: Application
    Filed: May 15, 2019
    Publication date: November 19, 2020
    Applicant: Powertech Technology Inc.
    Inventor: Kun-Yung Huang
  • Patent number: 10840200
    Abstract: A manufacturing method of a chip package structure includes: dicing a wafer to separate chips formed thereon; mounting the chips on a carrier, wherein an active surface and pads of each chip are buried in an adhesive layer disposed on the carrier, and a top surface of the adhesive layer between the chips is bulged away from the carrier; forming an encapsulant to encapsulate the chips and cover the adhesive layer, wherein the encapsulant has a concave surface covering the top surface of the adhesive layer and a back surface opposite to the concave surface; removing the carrier and the adhesive layer; forming a first dielectric layer to cover the concave surface and the active surface; forming a patterned circuit layer on the first dielectric layer, to electrically connect to the pads through openings in the first dielectric layer; and forming a second dielectric layer on the patterned circuit layer.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: November 17, 2020
    Assignee: Powertech Technology Inc.
    Inventors: Li-Chih Fang, Hung-Hsin Hsu, Nan-Chun Lin, Shang-Yu Chang Chien
  • Publication number: 20200357770
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a top semiconductor die, a bottom semiconductor die, a first encapsulant, a second encapsulant, a third encapsulant, a first redistribution layer and a second redistribution layer. The top semiconductor die is stacked on the bottom semiconductor die. The bottom semiconductor die is laterally encapsulated by the third encapsulant, and the third encapsulant is laterally surrounded by the first encapsulant. The top semiconductor die is laterally encapsulated by the second encapsulant. The first redistribution layer is disposed between the top and bottom semiconductor dies. The bottom semiconductor die, the first encapsulant and the third encapsulant are located between the first and second redistribution layers.
    Type: Application
    Filed: May 8, 2019
    Publication date: November 12, 2020
    Applicant: Powertech Technology Inc.
    Inventors: Chia-Wei Chiang, Li-Chih Fang, Wen-Jeng Fan
  • Publication number: 20200343184
    Abstract: A semiconductor package including a die stack, an insulating encapsulation encapsulating the die stack, a first redistribution layer (RDL) and a second RDL disposed on two opposite sides of the insulating encapsulation, and a through insulating via disposed aside the die stack and extending through the insulating encapsulation to be electrically connected to the first RDL and the second RDL. The die stack includes a first die and a second die stacked upon one another and electrically connected to the first die. The second die includes a through semiconductor via disposed therein. One of the first die and the second die includes conductive features having different thicknesses. The second RDL is connected to the through semiconductor via of the second die. A manufacturing method of a semiconductor package is also provided.
    Type: Application
    Filed: April 23, 2019
    Publication date: October 29, 2020
    Applicant: Powertech Technology Inc.
    Inventors: Hiroyuki Fujishima, Hung-Hsin Hsu, Shang-Yu Chang Chien, Nan-Chun Lin
  • Publication number: 20200343231
    Abstract: A package structure including a frame structure, a die, an encapsulant, a redistribution structure, and a passive component is provided. The frame structure has a cavity. The die is disposed in the cavity. The encapsulant fills the cavity to encapsulate the die. The redistribution structure is disposed on the encapsulant, the die, and the frame structure. The redistribution structure is electrically coupled to the die. The passive component is disposed on the frame structure and electrically coupled to the redistribution structure through the frame structure. A manufacturing method of a package structure is also provided. The frame structure may provide support, reduce warpage, dissipate heat from the die, act as a shield against electromagnetic interference, and/or provide electrical connection for grounding.
    Type: Application
    Filed: April 29, 2019
    Publication date: October 29, 2020
    Applicant: Powertech Technology Inc.
    Inventors: Shang-Yu Chang Chien, Hung-Hsin Hsu, Nan-Chun Lin
  • Publication number: 20200335456
    Abstract: A semiconductor package including a semiconductor chip, a conductive element disposed adjacent to the semiconductor chip, an insulating encapsulation covering the semiconductor chip and the conductive element, a redistribution structure disposed on the semiconductor chip and the conductive element, and a first buffer layer disposed between the redistribution structure and the insulating encapsulation is provided. The semiconductor chip is electrically coupled to the conductive element through the redistribution structure. The first buffer layer covers the semiconductor chip and the conductive element. A manufacturing method of a semiconductor package is also provided.
    Type: Application
    Filed: April 16, 2019
    Publication date: October 22, 2020
    Applicant: Powertech Technology Inc.
    Inventor: Wen-Jeng Fan
  • Publication number: 20200328161
    Abstract: A chip package structure including a first chip, an encapsulant, a first redistribution layer, a second redistribution layer, a second chip, and a third chip is provided. The first chip has an active surface, a back side surface opposite to the active surface, a plurality of conductive vias, and a plurality of conductive connectors disposed on the back side surface. The encapsulant covers the active surface, the back side surface, and the conductive connectors. The encapsulant has a first encapsulating surface and a second encapsulating surface opposite to the first encapsulating surface. The first redistribution layer is disposed on the first encapsulating surface. The second redistribution layer is disposed on the second encapsulating surface. The second chip is disposed on the second redistribution layer. The third chip is disposed on the second redistribution layer. A manufacturing method of a chip package structure is also provided.
    Type: Application
    Filed: March 25, 2020
    Publication date: October 15, 2020
    Applicant: Powertech Technology Inc.
    Inventors: Nan-Chun Lin, Hung-Hsin Hsu, Shang-Yu Chang Chien
  • Publication number: 20200328167
    Abstract: An integrated antenna package structure including a chip package and an antenna device is provided. The antenna device is disposed on the chip package. The chip package includes a chip, an encapsulant, a circuit layer, and a conductive connector. The encapsulant at least directly covers the back side of the chip. The circuit layer is disposed on the encapsulant and electrically connected to the chip. The conductive connector penetrates the encapsulant and is electrically connected to the circuit layer. The antenna device includes a dielectric body, a coupling layer, and an antenna layer. The dielectric body has a first dielectric surface and a second dielectric surface opposite to the first dielectric surface. The coupling layer is disposed on the second dielectric surface of the dielectric body. The antenna layer is disposed on the first dielectric surface of the dielectric body. The antenna layer is electrically connected to the conductive connector.
    Type: Application
    Filed: November 27, 2019
    Publication date: October 15, 2020
    Applicant: Powertech Technology Inc.
    Inventors: Shang-Yu Chang Chien, Hung-Hsin Hsu, Nan-Chun Lin
  • Publication number: 20200328144
    Abstract: A semiconductor package including a semiconductor chip, a conductive element disposed aside the semiconductor chip, a conductive via disposed on and electrically connected to the conductive element, an insulating encapsulation, and a first circuit structure disposed on the semiconductor chip and the conductive via is provided. A height of the conductive element is less than a height of the semiconductor chip. The insulating encapsulation encapsulates the semiconductor chip, the conductive element, and the conductive via. The conductive via is located between the first circuit structure and the conductive element, and the semiconductor chip is electrically coupled to the conductive via through the first circuit structure.
    Type: Application
    Filed: April 12, 2019
    Publication date: October 15, 2020
    Applicant: Powertech Technology Inc.
    Inventors: Wen-Jeng Fan, Shang-Yu Chang Chien, Nan-Chun Lin, Hung-Hsin Hsu