Abstract: An integrated antenna package structure including a chip, a circuit layer, an encapsulant, a coupling end, an insulating layer, a conductive connector, a dielectric substrate, and an antenna is provided. The circuit layer is electrically connected to the chip. The encapsulant is disposed on the circuit layer and covers the chip. The coupling end is disposed on the encapsulant. The insulating layer covers the coupling end. The insulating layer is not externally exposed. The conductive connector penetrates the encapsulant. The coupling end is electrically connected to the circuit layer by the conductive connection. The dielectric substrate is disposed on the encapsulant and covers the coupling end. The antenna is disposed on the dielectric substrate. A manufacturing method of an integrated antenna package structure is also provided.

Abstract: A method of detecting abnormal test signal channel of automatic test equipment firstly obtains a raw test data and then divides into the data groups according to a mapping data. The test data of DUTs in one data group are generated by the same group of probes. A yield of each data group is further estimated. A yield of a wafer is further estimated when the yield of the data group matches a first failure threshold. An abnormal test signal channel is determined when the yield of the wafer does not match a second failure threshold or the yield of the wafer matches the normal threshold. Therefore, to add the detecting method in an original test procedure of the ATE, the operator easily identifies which blocks in the failure color on the test data map are caused by the abnormal test signal channel.

Abstract: A semiconductor package structure includes a substrate, a chip, and an encapsulant. The chip is disposed on the substrate. The encapsulant is disposed on the substrate and covers the chip. The encapsulant has a top surface away from the substrate and at least one protruding strip protruding from the top surface.

Abstract: A manufacturing method of a package structure is described. The method includes at least the following steps. A carrier is provided. A semiconductor die and a sacrificial structure are disposed on the carrier. The semiconductor die is electrically connected to the bonding pads on the sacrificial structure through a plurality of conductive wires. As encapsulant is formed on the carrier to encapsulate the semiconductor die, the sacrificial structure and the conductive wires. The carrier is debonded, and at least a portion of the sacrificial structure is removed through a thinning process. A redistribution layer is formed on the semiconductor die and the encapsulant. The redistribution layer is electrically connected to the semiconductor die through the conductive wires.

Abstract: A semiconductor package with an internal heat sink has a substrate, a chip and an encapsulation. The substrate has an embedded heat sink, a first wiring surface and a second wiring surface. The embedded heat sink has a first surface and a second surface. The second wiring surface of the substrate and the second surface of the heat sink are coplanar. The chip has an active surface and a rear surface mounted on the first surface of heat sink through a thermal interface material layer and the active surface is electrically connected to the first wiring surface of the substrate. The encapsulation is formed on the first wiring surface of the substrate and the encapsulation encapsulates the chip. The heat generated from the chip is quickly transmitted to the heat sink and dissipated to air through the heat sink. Therefore, a heat dissipation performance of the semiconductor package is increased.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes first dies, an insulating encapsulation laterally encapsulating the first dies, a second die disposed over the portion of the insulating encapsulation and at least partially overlapping the first dies, and a redistribution structure disposed on the insulating encapsulation and electrically connected to the first dies and the second die. A second active surface of the second die faces toward first active surfaces of the first dies. The redistribution structure includes a first conductive via disposed proximal to the first dies, and a second conductive via disposed proximal to the second die. The first and second conductive vias are electrically coupled and disposed in a region of the redistribution structure between the second die and one of the first dies. The first conductive via is staggered from the second conductive via by a lateral offset.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first and a second active dies separately arranged, an insulating encapsulation at least laterally encapsulating the first and the second active dies, a redistribution layer disposed on the insulating encapsulation, the first and the second active dies, and a fine-pitched die disposed on the redistribution layer and extending over a gap between the first and the second active dies. The fine-pitched die has a function different from the first and the second active dies. A die connector of the fine-pitched die is connected to a conductive feature of the first active die through a first conductive pathway of the redistribution layer. A first connecting length of the first conductive pathway is substantially equal to a shortest distance between the die connector of the fine-pitched die and the conductive feature of the first active die.

Abstract: A method of fabricating a package structure including at least the following steps is provided. A carrier is provided. A first package is formed on the carrier. The first package is formed by at least the following steps. A first redistribution layer is formed on the carrier, wherein the first redistribution layer has a first surface and a second surface opposite to the first surface. A semiconductor die is bonded on the first surface of the first redistribution layer. The semiconductor die is electrically connected to the first redistribution layer through a plurality of conductive wires. An insulating material is formed to encapsulate the semiconductor die and the plurality of conductive wires.

Abstract: A package structure includes a redistribution structure, a bridge die, a plurality of conductive pillars, at least two dies, and an insulating encapsulant. The bridge die provides an electrical connection between the at least two dies. The conductive pillars provide an electrical connection between the at least two dies and the redistribution structure. The insulating encapsulant is disposed on the redistribution structure, encapsulates the bridge die and the conductive pillars, and covers each of the at least two dies. The bridge die of the package structure may be used to route signals between the at least two dies, allowing for a higher density of interconnecting routes between the at least two dies.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a bumpless die including a plurality of conductive pads, a conductive connector disposed aside the bumpless die and electrically coupled to the bumpless die, an insulating encapsulation encapsulating the bumpless die and the conductive connector, a circuit layer electrically connected to the bumpless die and the conductive connector, and a front side redistribution layer disposed on the circuit layer and including a finer line and spacing routing than the circuit layer. The circuit layer includes a conductive pattern disposed on the insulating encapsulation and extending along a thickness direction of the bumpless die to be connected to the conductive pads of the bumpless die, and a dielectric pattern disposed on the insulating encapsulation and laterally covering the conductive pattern.

Abstract: A fan-out package with warpage reduction has a redistribution layer (RDL), at least one bare chip and a multi-layer encapsulation. A plurality of metal bumps on an active surface of each bare chip are respectively and electrically connected to a plurality of inner pads of the RDL. The multi-layer encapsulation is formed on the RDL to encapsulate the least one bare chip and at least has two different encapsulation layers with different coefficient of thermal expansions (CTE) to encapsulate different portions of sidewalls of each bare chip. One of the encapsulation layers with the smallest CTE is close to RDL. Therefore, in a step of forming the multi-layer encapsulation at high temperature, the suitable CTEs of the encapsulation layers are selected to reduce a warpage between the encapsulation layer and a material layer thereto.

Abstract: A stacked package structure has a metal casing, a stacked chipset, an encapsulation and a redistribution layer. The stacked chipset is adhered in the metal casing. The encapsulation is formed in the metal casing to encapsulate the stacked chip set, but a plurality of surfaces of the metal pads are exposed through the encapsulation. The redistribution layer is further formed on the encapsulation and electrically connects to the metal pads of the stacked chipset. Therefore, the stacked package structure includes the metal casing, so an efficiency of heat dissipation and structural strength are increased.

Abstract: A method of detecting abnormal test signal channel of automatic test equipment firstly obtains a raw test data and then divides into the data groups according to a mapping data. The test data of DUTs in one data group are generated by the same group of probes. A yield of each data group is further estimated. A yield of a wafer is further estimated when the yield of the data group matches a first failure threshold. An abnormal test signal channel is determined when the yield of the wafer does not match a second failure threshold or the yield of the wafer matches the normal threshold. Therefore, to add the detecting method in an original test procedure of the ATE, the operator easily identifies which blocks in the failure color on the test data map are caused by the abnormal test signal channel.

Abstract: A manufacturing method of a stacked chip package structure includes the following steps. A first chip is disposed on a carrier, wherein the first chip has a first active surface and a plurality of first pads disposed on the first active surface. A second chip is disposed on the first chip without covering the first pads and has a second active surface and a plurality of second pads disposed on the second active surface. A plurality of first stud bumps are formed on the first pads. A plurality of pillar bumps are formed on the second pads. The first chip and the second chip are encapsulated by an encapsulant, wherein the encapsulant exposes a top surface of each second stud bump. A plurality of first vias are formed by a laser process, wherein the first vias penetrate the encapsulant and expose the first stud bumps. A conductive layer is formed in the first vias to form a plurality of first conductive vias. The carrier is removed.

Abstract: A method of fabricating a package structure including at least the following steps is provided. A carrier is provided. A first package is formed on the carrier. The first package is formed by at least the following steps. A first redistribution layer is formed on the carrier, wherein the first redistribution layer has a first surface and a second surface opposite to the first surface. A semiconductor die is bonded on the first surface of the first redistribution layer. The semiconductor die is electrically connected to the first redistribution layer through a plurality of conductive wires. An insulating material is formed to encapsulate the semiconductor die and the plurality of conductive wires.

Abstract: A manufacturing method of a package structure is described. The method includes at least the following steps. A carrier is provided. A semiconductor die and a sacrificial structure are disposed on the carrier. The semiconductor die is electrically connected to the bonding pads on the sacrificial structure through a plurality of conductive wires. As encapsulant is formed on the carrier to encapsulate the semiconductor die, the sacrificial structure and the conductive wires. The carrier is debonded, and at least a portion of the sacrificial structure is removed through a thinning process. A redistribution layer is formed on the semiconductor die and the encapsulant. The redistribution layer is electrically connected to the semiconductor die through the conductive wires.

Abstract: A package structure including a semiconductor die, an insulating encapsulant, a dielectric layer, and a redistribution layer is provided. The semiconductor die has an active surface, a back surface opposite to the active surface, and a plurality of conductive bumps disposed on the active surface. The insulating encapsulant is encapsulating the semiconductor die. The redistribution layer is disposed on the he insulating encapsulant and electrically connected to the plurality of conductive bumps. The dielectric layer is disposed between the insulating encapsulant and the redistribution layer, wherein the dielectric layer encapsulates at least a portion of each of the plurality of conductive bumps.

Abstract: A package structure includes a die, an encapsulant, a dam structure, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The encapsulant encapsulates sidewalls of the die. The encapsulant has a first surface and a second surface opposite to the first surface. The first surface is coplanar with the rear surface of the die. The second surface is located at a level height different from the active surface of the die. The dam structure is disposed on the active surface of the die. A top surface of the dam structure is substantially coplanar with the second surface of the encapsulant. The redistribution structure is over the encapsulant, the dam structure, and the die. The redistribution structure is electrically connected to the die.

Abstract: A testing device includes a transfer interface, a tester, a first socket group and a second socket group. The first socket group includes a plurality of tested devices coupled in series and the second socket group includes a plurality of tested devices coupled in series. The tester is electrically connected to the socket group via the transfer interface. The transfer interface is configured to merge a first testing signal with a second testing signal to generate a double frequency testing signal. The double-frequency testing signal and a plurality of control signals are provided to the tested devices in the first socket group and the second socket group to perform the testing procedure on the tested devices of a same tested device pair simultaneously, and performing the testing procedure on the tested device pairs sequentially.

Abstract: A package structure including a die, a plurality of first conductive connectors, a second conductive connector electrically insulated from the die, a redistribution layer and a conductive shield is provided. The die includes an active surface, a back surface opposite the active surface, and a sidewall coupling the active surface to the back surface. The first conductive connectors are disposed on the active surface of the die and electrically connected to the die. The second conductive connector is disposed on the die and aside the first conductive connectors. The redistribution layer is disposed on the die and electrically connected to the first conductive connectors and the second conductive connector. The conductive shield coupled to the redistribution layer surrounds the second conductive connector and at least a portion of the sidewall. The die is electrically insulated to the conductive shield. A chip package structure is also provided.