Abstract: A package structure includes a die, an encapsulant, a dam structure, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The encapsulant encapsulates sidewalls of the die. The encapsulant has a first surface and a second surface opposite to the first surface. The first surface is coplanar with the rear surface of the die. The second surface is located at a level height different from the active surface of the die. The dam structure is disposed on the active surface of the die. A top surface of the dam structure is substantially coplanar with the second surface of the encapsulant. The redistribution structure is over the encapsulant, the dam structure, and the die. The redistribution structure is electrically connected to the die.

Abstract: A package structure includes a first redistribution layer, a second redistribution layer, a die, a plurality of conductive pillars and a die-stacked structure. The first redistribution layer has a first surface and a second surface opposite to the first surface. The second redistribution layer is disposed above the first surface. The die is disposed between the first redistribution layer and the second redistribution layer and has an active surface and a rear surface opposite to the active surface. The active surface is adhered to the first surface, and the die is electrically connected to the first redistribution layer. The conductive pillars are disposed and electrically connected between the first redistribution layer and the second redistribution layer. The die-stacked structure is bonded on the second redistribution layer.

Abstract: A semiconductor package including a stacked-die structure, a second encapsulant laterally encapsulating the stacked-die structure and a redistribution layer disposed on the second encapsulant and the staked-die structure is provided. The stacked-die structure includes a first semiconductor die including a first active surface, a circuit layer disposed on the first active surface, a second semiconductor die including a second active surface facing towards the first active surface, a plurality of conductive features distributed at the circuit layer and electrically connected to the first and second semiconductor die and a first encapsulant encapsulating the second semiconductor die and the conductive features. A portion of the conductive features surrounds the second semiconductor die. The redistribution layer is electrically connected to the staked-die structure. A manufacturing method of a semiconductor package is also provided.

Abstract: A chip package structure includes a redistribution layer, at least one chip, a reinforcing frame, an encapsulant and a plurality of solder balls. The redistribution layer includes a first surface and a second surface opposite to each other. The chip is disposed on the first surface and electrically connected to the redistribution layer. The reinforcing frame is disposed on the first surface and includes at least one through cavity. The chip is disposed in the through cavity and a stiffness of the reinforcing frame is greater than a stiffness of the redistribution layer. The encapsulant encapsulates the chip, the reinforcing frame and covering the first surface. The solder balls are disposed on the second surface and electrically connected to the redistribution layer.

Abstract: A manufacturing method of a package structure is provided. The method includes the following steps. A semiconductor chip is bonded on a carrier, wherein the semiconductor chip comprises a plurality of conductive pads. An insulating material layer is formed over the carrier and encapsulating the semiconductor chip, wherein a thickness of the insulating material layer is greater than a thickness of the semiconductor chip. A first surface of the insulating material layer is patterned to form first openings that expose the conductive pads of the semiconductor chip, and second openings that penetrate through the insulating material layer. A plurality of conductive posts is formed in the first openings, wherein the plurality of conductive posts is electrically connected to the plurality of conductive pads of the semiconductor chip. A plurality of conductive vias is formed in the second opening.

Abstract: A wafer processing method uses a chuck table with smaller diameter than a semiconductor wafer to be processed. A cut through edge trimming is therefore implemented on the periphery of the semiconductor wafer to form a cut through straight side at the periphery and also form a flat portion at the periphery as a positioning means for taping and backside grind processes.

Abstract: A chip package structure including a first circuit structure, a chip, an electronic device, a first encapsulant, a second encapsulant, a plurality of through pillars, and an electromagnetic interference (EMI) shielding layer is provided. The chip has an active surface facing the first circuit structure. The electronic device has a connection surface facing the first circuit structure. The chip and the electronic device are disposed on opposite sides of the first circuit structure respectively. The first encapsulant encapsulates the chip. The second encapsulant encapsulates the electronic device. The through pillars penetrate the first encapsulant and are electrically connected to the first circuit structure. The EMI shielding layer covers the first encapsulant and the second encapsulant. The chip or the electronic device is grounded by the EMI shielding layer.

Abstract: A testing method of a packaging process includes following steps. A substrate is provided. A circuit structure is formed on the substrate. The circuit structure includes a real unit area and a dummy side rail surrounding the real unit area, and a plurality of first circuit patterns is disposed on the real unit area. A second circuit pattern is formed on the dummy side rail, and the second circuit pattern emulates the configurations of at least a portion of the first circuit patterns for operating a simulation test. In addition, a packaging structure adapted for a testing process is also mentioned.

Abstract: A semiconductor package including a redistribution layer, semiconductor devices, a semiconductor die, conductive features, an encapsulant and conductive terminals is provided. The semiconductor devices are disposed on the first surface of the redistribution layer. The semiconductor die, the conductive features, the encapsulant including openings are disposed on the second surface of the redistribution layer. The semiconductor die is embedded in the encapsulant, and the portion of the conductive features is protruded from the encapsulant. The conductive terminals including first elements disposed in the openings of the encapsulant and second elements disposed on the conductive features. A portion of the first elements and the second elements are protruded from the encapsulant, and a surface of each of the first elements opposite to the encapsulant and a surface of each of the second elements are aligned with a standoff baseline. A manufacturing method of semiconductor package is also provided.

Abstract: A laser color marking method for a semiconductor package has steps of: (a) providing a semiconductor element; (b) sputtering a metal layer on the semiconductor element; (c) obtaining a marking pattern; and (d) applying a laser light source on the marking region to form a mark according to the marking pattern. The mark is consisted of an optical oxide film converting ambient light to a corresponding color light, so a visible color mark is marked. Therefore, the present invention easily laser-marks the visible color mark on the semiconductor package.

Abstract: A stacked package has plurality of chip packages stacked on active surfaces of each other, a dielectric layer, a redistribution layer and a plurality of external terminals. Each chip package has an exterior conductive element formed on the active surface. Each exterior conductive element has a cut edge exposed on at least one of the lateral side of the chip package. The dielectric layer, the redistribution layer and the external terminals are formed in sequence on the lateral side with the exposed cut edges to form the electrical connection between the cut edges, the redistribution layer and the external terminals. Therefore, the process for forming the electrical connections is simplified to enhance the reliability and the UPH for manufacturing the stacked package.

Abstract: A stacked package has plurality of chip packages stacked on a base. Each chip package has an exterior conductive element formed on the active surface. Each exterior conductive element has a cut edge exposed on a lateral side of the chip package. The lateral trace is formed through the encapsulant and electrically connects to the cut edges of the chip packages. The base has an interconnect structure to form the electrical connection between the lateral trace and the external terminals. Therefore, the process for forming the electrical connections is simplified to enhance the reliability and the UPH for manufacturing the stacked package.

Abstract: A semiconductor package including a stacked-die structure, a second encapsulant laterally encapsulating the stacked-die structure and a redistribution layer disposed on the second encapsulant and the staked-die structure is provided. The stacked-die structure includes a first semiconductor die including a first active surface, a circuit layer disposed on the first active surface, a second semiconductor die including a second active surface facing towards the first active surface, a plurality of conductive features distributed at the circuit layer and electrically connected to the first and second semiconductor die and a first encapsulant encapsulating the second semiconductor die and the conductive features. A portion of the conductive features surrounds the second semiconductor die. The redistribution layer is electrically connected to the staked-die structure. A manufacturing method of a semiconductor package is also provided.

Abstract: A stacked package has plurality of chip packages stacked on active surfaces of each other, a dielectric layer, a redistribution layer and a plurality of external terminals. Each chip package has an exterior conductive element formed on the active surface. Each exterior conductive element has a cut edge exposed on at least one of the lateral side of the chip package. The dielectric layer, the redistribution layer and the external terminals are formed in sequence on the lateral side with the exposed cut edges to form the electrical connection between the cut edges, the redistribution layer and the external terminals. Therefore, the process for forming the electrical connections is simplified to enhance the reliability and the UPH for manufacturing the stacked package.

Abstract: A manufacturing method of a packaging structure is provided. First, a carrier is provided. A conductive layer is formed on the carrier. A conductive frame is formed on the conductive layer. The conductive frame is in contact with and electrically connected to the conductive layer. A chip is placed on the conductive layer. The conductive frame surrounds the chip. An insulation encapsulation is formed to encapsulate the chip, and the insulation encapsulation exposes an active surface of the chip. A redistribution layer is formed on the active surface of the chip. The redistribution layer extends from the active surface to the insulation encapsulation.

Abstract: A manufacturing method of a package structure is provided. The method includes the following steps. A package panel is provided. The package panel includes a first encapsulation, a plurality of first integrated circuit components and a plurality of redistribution circuit patterns electrically connected to the first integrated circuit components, the first integrated circuit components are encapsulated by the first encapsulation, and the redistribution circuit patterns are distributed on the first encapsulation and the first integrated circuit components. The first encapsulation of the package panel is cut to form a plurality of singulated package strips. One of the singulated package strips is attached onto an attachment region of a substrate. The substrate includes at least one tooling hole distributed outside of the attachment region. The package process is performed over the singulated package strip with the substrate affixed through the tooling hole to form the package structure.

Abstract: A package structure including a redistribution structure, a die, a plurality of conductive structures, a first insulating encapsulant, a chip stack, and a second insulating encapsulant. The die is disposed on and electrically connected to the redistribution structure. The conductive structures are disposed on and electrically connected to the redistribution structure. The conductive structures surround the die. The first insulating encapsulant encapsulates the die and the conductive structures. The first insulating structure includes a plurality of openings exposing top surfaces of the conductive structures. The chip stack is disposed on the first insulating encapsulant and the die. The chip stack is electrically connected to the conductive structures. The second insulating encapsulant encapsulates the chip stack.

Abstract: A package structure including a redistribution structure, a die, at least one connecting module, a first insulating encapsulant, a chip stack, and a second insulating encapsulant. The die is disposed on and electrically connected to the redistribution structure. The connecting module is disposed on the redistribution structure. The connecting module includes a protection layer and a plurality of conductive bars embedded in the protection layer. The first insulating encapsulant encapsulates the die and the connecting module. The chip stack is disposed on the first insulating encapsulant and the die. The chip stack is electrically connected to the connecting module. The second insulating encapsulant encapsulates the chip stack.

Abstract: A package structure including a redistribution structure, a die, at least one connecting module, a first insulating encapsulant, a chip stack, and a second insulating encapsulant. The die is disposed on and electrically connected to the redistribution structure. The connecting module is disposed on the redistribution structure. The connecting module has a protection layer and a plurality of conductive bars. The conductive bars are embedded in the protection layer. The protection layer includes a plurality of openings corresponding to the conductive bars. The first insulating encapsulant encapsulates the die and the connecting module. The chip stack is disposed on the first insulating encapsulant and the die. The chip stack is electrically connected to the connecting module. The second insulating encapsulant encapsulates the chip stack.

Abstract: A manufacturing method of a package structure is provided. The method includes the following steps. A package panel is provided. The package panel includes a first encapsulation, a plurality of first integrated circuit components and a plurality of redistribution circuit patterns electrically connected to the first integrated circuit components, the first integrated circuit components are encapsulated by the first encapsulation, and the redistribution circuit patterns are distributed on the first encapsulation and the first integrated circuit components. The first encapsulation of the package panel is cut to form a plurality of singulated package strips. One of the singulated package strips is attached onto an attachment region of a substrate. The substrate includes at least one tooling hole distributed outside of the attachment region. The package process is performed over the singulated package strip with the substrate affixed through the tooling hole to form the package structure.