Abstract: The invention comprises a write buffer system which provides residence time information that increases the merge potential and enhances the write collapse feature of a "smart" buffer. The write buffer has multiple buffer locations for storing data received from a central processor, a data merger for merging data designated by the central processor for subsequent storage in contiguous memory locations, and a write controller for selectively writing the data from the plurality of write buffer locations to the memory. The system further includes time stamp registers in communication with the write controller for storing and updating a time signal representative of the write buffer location having most recently received data. The controller is responsive in part to the time signal, and inhibits the writing to memory of the data in the write buffer location having most recently received data since this is the location most likely to be eligible for a data merge.

Abstract: A method for transfer of data between multiple tasks in a host computer and multiple tasks in an intelligent controller. One or more memory buffers for holding the data to be transferred are allocated to each task. Each connection between corresponding tasks in the host and the controller is provided with a set of queues for controlling access by the controller to the memory buffers. An output queue contains descriptions of output buffers holding data for transfer from the host to the controller. A buffer queue contains descriptions of input buffers available for transfer of data from the controller to the host, a return queue contains descriptions of output buffers available for transfer of data from the host to the controller, and an input queue contains descriptions of input buffers holding data that has been transferred from the controller to the host. The queues contain pointers to extended control blocks, each containing a virtual data pointer and a physical data pointer to a specified buffer.

Abstract: A technique for providing skew compensation particularly in association with a pipelined processor. The skew occurs between first and second clock signals. The skew compensation technique of the invention provides for the proper transfer of information between stages even though the clock signals may have a skew greater than the inter-stage delay. A holding or latching means is provided between stages so as to hold the previous stage data for clocking into the subsequent stage register.

Abstract: A method and apparatus for accessing a selected entry in a first memory by means of an index formed by combining an index and a stored backpointer of a second memory's entry corresponding to the selected entry in the first memory.

Abstract: A license storage key is provided for securely storing information regarding which licenses have been purchased for a network of computers, how many of each license have been purhcased, and any time limits associated with each license. An application program to be run on a computer must be assigned a license in the license storage key associated with the computer before it will be permitted to run. If a license cannot be found on the local key, a license may be found on another key in the network of computers and transferred to the local key so that the application program may be run in this case, when the license is released. The license storage key contains a hardware clock which is used to determine whether a license has expired.

Abstract: A system for correcting soft memory failures such as alpha particle failures in a dynamic random access memory and in a computer system wherein writeback caches are employed in a system bus environment. The address field and source identification code associated with a detected data error are stored. A generic bus request signal is generated and upon a bus grant a read message is issued on the system bus having an address field and destination address code corresponding to the stored address field and source identification code. In response to the read message, the device indicated by the identification code writes back to memory the correct data corresponding to the address field.

Abstract: In a computer system in which addressable components are physically organized on separately-replaceable printed circuit boards each containing an array of separately addressable components, diagnostic apparatus operates in the event of a component failure to assist a technician in physically locating the circuit board which contains the failed component. Each array includes a selection circuit which responds to component addresses located in the component array on that board. In the case of a component failure, diagnostic circuitry detects the address of the faulty component and places the address on the system address bus. The diagnostic circuitry controls each array to forward the output signal from the selection circuit on the associated printed circuit board to a register which has a position associated with each printed circuit board.

Abstract: A method of filling a polygon as represented on a scan-line raster display includes storing data representative of the polygon edges, computing the points of intersection of a scan-line with each polygon edge, assigning a count having a parity value to each crossed-edge, and combining all colinear horizontal edges at the points of intersection. The number of polygon edges positioned above the colinear horizontal edge and which have a vertex coincident with the colinear horizontal edge, as well as the number of polygon edges positioned below the colinear horizontal edge and which have a vertex coincident with the colinear horizontal edge, are calculated. The parity of the crossed-edge count is inverted if the parity of both the above edge count and below edge count are even, and the string of pixels along the raster display scan-line from the current edge intersection to the next edge intersection are modified if the parity of the crossed-edge count is odd.

Abstract: A look ahead fetch system for a pipelined digital computer is provided for predicting in advance of decoding the outcome of a branch instruction. The system includes a branch cache having a plurality of associative sets for storing branch target addresses indexed by the lowest significant bits of the corresponding branch instruction's address. A memory for storing a coupling bit vector indicative for each branch cache set of whether the set contains a corresponding branch target address. The coupling bit vector is used to guide prediction logic to the correct branch cache sets for qualifying the entry there contained having an index corresponding to a fetched instruction's address for formulating a prediction of the next instruction to be processed.

Abstract: A system for controlling the addressing of a memory on a predetermined multi-megabyte decode boundary. An address shifter is coupled between CPU address lines and backplane area bussed address lines. The address shifter is controlled in accordance with the control signal determined by the memory array of largest capacity of all memory arrays. The control signal has different states to control the address shifter to couple different address bit patterns therethrough to the backplane area address bus as a function of the selected control signal state.

Abstract: A disk control system offloads to the disk controller much of the overhead associated with disk operations and makes the CPU available for other work. A command block that fully specifies a user request for a disk operation is forwarded to the disk memory unit. The command block contains a unique identifier for tracking of user requests. User requests are executed by the disk memory unit in an order that is most efficient for the disk drive system. The status of a user request is communicated to the CPU via an interrupt and a status block containing the unique identifier. The status block indicates status conditions such as command read, completion and DMA channel request. The disk driver contains a work queue for user requests that have not been forwarded to the disk memory unit and a pending queue for user requests that are awaiting completion by the disk memory unit. By manipulation of the work queues and pending queues, the disk controller can be automatically reinitialized when an error occurs.

Abstract: Methods and apparatus for accurately measuring propagation delay through very high speed VLSI devices with a test instrument having errors comparable to the delays being measured. The VLSI device has a plurality of parallel operational signal paths, each with a very short propagation delay. The VLSI device is fabricated with control circuitry for selectively connecting the parallel operational signal paths in series in a test mode so as to define a test signal path comprising multiple operational signal paths. The test signal path has a relatively long propagation delay which can be measured with acceptable accuracy by the test instrument. The test signal path is defined so that it bypasses clocked circuit elements on the VLSI device. Since the operational signal paths are on the same integrated circuit and have very well correlated operating characteristics, the propagation delay through the test signal path is a good representation of the integrated circuit dynamic operation.

Abstract: Control apparatus allows application software written for use with peripheral devices manufactured by one company to run with other peripheral devices. The apparatus intercepts device-specific control commands generated by the software and translates the commands into commands which are compatible with the peripheral connected to the system. Non-device specific commands are passed untranslated through the control apparatus to the peripheral. More specifically, registers within the control apparatus which must be programmed with parameters unique to a particular peripheral cannot be accessed by the application software while other nonspecific registers remain read and write accessible. Peripheral-specific parameters are instead changed by a secondary processor which uses special hardware to minimize interference with the main processor.

Abstract: A branch cache system for use with a pipelined processor having overlapping parcel prefetch and execution stages. The system includes a plurality of memory sets for storing a plurality of indexed sets of predicted branch addresses, and control circuitry which determines whether there is stored in one of the memory sets a predicted branch address which corresponds to a branch instruction fetched by the prefetch stage. The execution stage is commanded, responsive to detection of a predicted branch address corresponding to that branch instruction, to execute the branch instruction to the predicted branch address. Alternatively, the system includes one or more memory sets for storing predicted branch addresses and corresponding alignment values which represent whether the boundary of a prefetched branch instruction, which is prefetched as one or more parcels, aligns with the fixed boundary of the one or more parcels containing that instruction.

Abstract: A Hashing Indexer For a Branch Cache for use in a pipelined digital processor that employs macro-instructions utilizing interpretation by micro-instructions. Each of the macro-instructions has an associated address and each of the micro instructions has an associated address. The hashing indexer includes a look-ahead-fetch system including a branch cache memory coupled to the prefetch section. An indexed table of branch target addressess each of which correspond to the address of a previously fetched instruction is stored in the branch cache memory. A predetermined number of bits representing the address of the macro-instruction being fetched is hashed with a predetermined number of bits representing the address of the micro-instruction being invoked. The indexer is used to apply the hashing result as an address to the branch memory in order to read out a unique predicted branch target address that is predictive of a branch for the hashed macro-instruction bits and micro-instruction bits.

Abstract: A semiconductor chip carrier package formed of a multi-layer circuit board having mounted therein a semiconductor chip support pad. The multi-layer circuit board is comprised of separate dielectric boards defining multiple conductive run layers including a signal layer and a plurality of power layers. A pluralilty of pins supported from the circuit board extending from one side thereof and including signal pins and power pins. The power pins are disposed peripherally outside of the signal pins. Means are provided for conductively connecting leads of the semiconductor chip to corresponding conductive runs of the signal and power layers.

Abstract: A method of performing an input/output process containing a programmed input/output (PIO) instruction in a multiprocessor system including at least two processors each having an associated I/O bus with I/O devices connected thereto. The method has the steps of storing a unique address and a bus location for each I/O device in a device location table, determining the address of a referenced I/O device prior to performing the PIO instruction, reading the corresponding I/O bus location of the referenced I/O device from the device location table and executing the input/output process on the prescribed processor associated with the I/O bus to which the referenced I/O device is located. The method is used in conjunction with a task scheduler including a process control block for each scheduled process. When the PIO instruction references a device on the local I/O bus, the input/output process is executed normally.

Abstract: A digital computer system adapted for executing a set of instructions including at least one encrypted instruction. The system includes a main memory for storing the instructions, a cache memory for storing selected instructions with a relatively fast access time, a selectively operable decryption system for decrypting selected encrypted instructions from the main memory, and a central processing unit. The system is adapted so that the program stored in the main memory may be executed by the central processing unit. To this end, the decrypted instructions are decrypted only during execution when those instructions are transferred from the main memory to the cache memory so that plaintext versions of those encrypted instructions exist only in the cache memory in response to requests by the central processing unit while executing the program.

Abstract: A variable thickness intermediate cooling member adapted to be disposed between a circuit board having electronic module or packages mounted thereon and a cold plate providing thermal coupling between the cold plate and the circuit board. The intermediate cooling member is comprised of a foldable heat conductive member having a manually operable handle for moving the member between a maximum thickness circuit board engaging position to provide thermal contact, and a minimum thickness circuit board disengaging position to enable access to the circuit board.

Abstract: When data is subject to relocation in the physical memory of a processing system employing a virtual memory architecture, execution of programs can be greatly improved through the use of a validation code generator, which assigns a code to each virtual-to-physical address translation prior to its entry in the address translation system. Whenever a page in memory is replaced or the buffer is purged for memory management purposes, the code generator proceeds to another code and assigns this new code to subsequent entries.