Abstract: The present invention is directed to a hardware authentication system for a public key communications network. The public key network includes at least one user terminal and at least one hardware authentication terminal coupled by a communications medium. The authentication terminal generates and stores a plaintext message M, and generates from this message M a ciphertext message C by transforming the plaintext message M with the public key of the user terminal. The authentication terminal is further adapted to transmit the ciphertext message C by way of the medium to the user terminal.The user terminal is adapted to receive the enciphered or ciphertext message C from the hardware authentication terminal, and transform that ciphertext message with its private key to obtain a plaintext message M'. The user terminal is further adapted to transmit the plaintext message M' by way of the medium to the authentication terminal.

Abstract: A range transformation method for transforming the normalized divisor in a division calculation to a range wherein the transformed value differs from one by no more than the quantity 2.sup.-n. The method and apparatus generate the transform multiplier value from a first high order "q" digits of the divisor and generate an out-of-range indicator signal from at least those same digits. The thus generated multiplier value is modified in response to the out-of-range indicator signal when an out-of-range condition is indicated. The apparatus employs a read-only-memory for enabling the generation of the transform multiplier value without requiring either large table look-up storage or multiplicative functions. As a result, various division methods requiring an initial transformation to provide a divisor which approaches one in value can be efficiently implemented.

Abstract: A system for transferring solicited message packets between data processors coupled on a serial communications path. A solicitor processor includes a receiver message processor adapted to allocate portions of the solicitor processor memory for storing the header portions of received solicited and unsolicited data packets. The receive message processor identifies solicited data packets. For those message packets, predetermined allocated locations in the solicitor processor memory are identified from sub-portions of the header portions, and the data portions of those packets are then stored in the identified locations. Unsolicited data packets are identified as such, and are processed conventionally.

Abstract: A digital system simulation apparatus and method to enable a user to interactively control, during simulation, sampling of signals in the digital system whose behavior is being simulated. The behavior of the system can be approximated by recognizing and displaying the circuit element inputs and outputs. Breakpoints can also be set, interactively, during simulation, for controlling initiation and termination of the sampling process. The method and apparatus can also sample upon the Nth occurrence of a specified condition.

Abstract: A controller for use with a magnetic tape drive which has a plurality of buffer memories for temporarily storing data that is passed between the tape drive and a host computer system. Temporary storage of data within the tape controller allows data to be rewritten on the tape if the initial writing is faulty and allows data read from the tape to be reconstructed if the data has been erroneously recorded.Transfer of information into and out of the buffer circuits is controlled by two independent direct memory access circuits--one circuit transfers data between the host computer system and the buffer memories and the other circuit transfer data between the buffer memories and the tape drive. Each of the direct memory access circuits operates independently of the other, however, both circuits are coordinated by a central processing unit which communicates with the direct memory access units by means of an interrupt arrangement.

Abstract: A digital logic bus termination module that is to be plugged into a TTL logic backplane bus and in which the module includes a TTL logic circuit chip package having multiple terminals including a reference terminal, input terminal and output terminal. The TTL logic circuit chip package comprises an input diode, preferably a Schottky diode connected to the input terminal thereof and forming a bus termination clamping means. The bus line is connected to the input terminal of the chip package while the bus reference line is coupled to the reference or ground terminal for the circuit chip package. The TTL logic circuit chip package has the output terminal thereof unconnected so that only the diode is in operative association with the bus. One or more resistors may also be used in parallel with the clamping diodes for impedance matching purposes.

Abstract: An anticipatory power failure detection apparatus and method, for use in connection with power supplies providing a regulated voltage signal to an electronic load such as a computer, employing circuitry for determining whether a control signal, within the regulated power supply circuit, is in a saturation state. Upon detecting a saturation state for the control signal, circuitry signals that an input power failure is occurring. The regulated power supply system can be a switching-type voltage regulation control system, wherein a pulse-width modulated switching system controls the periodic input of energy to an energy-storage network which generates the regulated voltage output signal. A derivative of the error signal is periodically sampled for determining whether it is in the saturation state. The regulated power supply control signal will be in the saturation state when the unregulated input voltage supply is insufficient to maintain the regulated voltage signal at the specified optimum operating point.

Abstract: A semiconductor termination socket for use with a printed wiring board has a mounting socket base for attachment to the board and plural pin socket receiving elements in the base for connecting to leads of a semiconductor chip package which will be removably inserted into the socket. The socket further has electrical components fabricated within the socket base for connecting a pin of the socket and a termination potential. The electrical components are preferably fabricated using planar technology so that the socket becomes, in essence, a printed wiring board. The semiconductor packages can be of any configuration including, for example, 149 pin grid array packages. If more than one layer of component circuitry is needed, a plurality of layers can be embedded within the mounting socket.

Abstract: Digital circuitry performs arithmetic operations upon first and second binary coded decimal digit strings input thereto. The digital circuitry provides for receiving and storing a first and second BCD digit, the digits having an arbitrary data type format. The first and second data types are selected from the group of packed and unpacked data. The circuitry then performs the arithmetic operation upon the stored BCD digits to obtain a result data word which is made available in a data type format corresponding to a selected one of the input BCD digits. In a particular embodiment, a plurality of the circuits can be operated in a digit slice structure. The digit slice structure operates upon strings of packed, unpacked, and mixed data type arithmetic operands and provides, at its output lines, output data in a format corresponding to a selected input data type. In particular, a unique interconnection of the plural output lines of the circuitry enables the output data type to be packed or unpacked as desired.

Abstract: An apparatus and method for detecting an AC power failure condition employs a fast attack, slow decay, energy storage circuit for tracking an AC input signal and for providing a slowly decaying output based upon a last received peak voltage input value. A current detection circuit monitors the current flow to the storage circuit from the AC mains and generates a current detection signal in response thereto. A power failure condition is declared when either the voltage across the energy storage circuit decays below a selected threshold value or current is not detected flowing to the energy storage circuit at a selected time. A particular current detection circuit employs a high permeability core which is saturated by a current in the sensed line having a current value below an expected peak current flowing to the energy storage circuit. An interrogation pulse periodically energizes an interrogation winding which, in the absence of current in the sensed line, induces a signal across an output winding.

Abstract: The invention features a method and apparatus for improving data transmission in a transmission system having an analog signal transmitter directly connected along a transmission link to an analog signal receiver having a threshold element for detecting the signal. The invention features clamping voltages appearing at an input of the receiver symmetrically about a threshold value of the threshold element.

Abstract: Controller circuitry for a serially-recording magnetic tape drive which is capable of correcting writing errors by rewriting the portions of the data which have been erroneously recorded. Write circuitry in the controller breaks a conventional data record up into one or more blockettes, each of which is assigned a unique sequential blockette number which is recorded on the tape along with the data. After each blockette has been serially recorded sequentially by blockette number on the tape, it is immediately read to check whether it has been properly recorded on the tape. If the blockette has been recorded improperly, the read process directs the write circuitry to rerecord the blockette information at the tape position then under the write head. The recorded blockettes may be out of sequential order since the rerecorded blockette may be located several blockettes after its initial erroneous writing. The data is placed back in sequential order by the read process.

Abstract: A digital system simulation apparatus and method enable better efficiency and precision of system simulation by operating in either a four signal-level mode or a nine signal-level mode, depending upon the particular circuitry being employed. All signal outputs are generated in the nine signal-level mode, however, when the output is directed to a gate level circuit element, the apparatus and method automatically mask the strength data in the output signal thereby providing the four signal-level mode of operation.

Abstract: A system for transferring solicited message packets between data processors coupled on a serial communications path. A solicitor processor allocates a portion of its memory for storage of solicited message packets which might be solicited and received from at least one other data processor. The solicitor data processor defines a sequence of operations to be performed on any such received solicited message packets at that processor. The solicitor processor also transfers a solicited message parameter signal to the solicitee data processor where that signal is representative of a predetermined header portion for solicited data packets which might be generated by the solicitee data processor and transferred to the solicitor data processor. The header portion of a solicited message packet relates one or more of the sequences of operations which are to be associated with that packet.

Abstract: A token-passing ring network, having a plurality of nodes connected to a bus loop, employs multiplexing circuitry for connecting each node to the bus on at least one of a plurality of simultaneously operating bus channels. Each bus channel operates independently of each other bus channel and each channel has associated therewith, its own token. The multiple channels are arranged on a single transmission medium and an amplitude multiplexing receiver and transmitter circuitry provide the plurality of channels on the medium.

Abstract: A ring communications network which is automatically reconfigured based on the detection of system defects.

Abstract: An apparatus and method, for connecting a node to and disconnecting a node from a high speed data communications network, has a dead man switching element and high speed solid state switching circuitry interconnected therewith to avoid the effects of mechanical contact bounce normally associated with operation of the mechanical switching element. Thereby, massive data losses on high speed communications paths, and token loss in a token-passing ring network, are substantially avoided. The switch has the solid state switching circuitry connected both in parallel and in series with its mechanical contacts for providing node isolation and communications path bypass channels during the time that the mechanical switch bounce occurs. The alternate paths are maintained during a change of state of the mechanical device, that is, when the node is being connected or disconnected from the communications network.

Abstract: An address translation method and apparatus is disclosed for use in an auxiliary memory of a computer, which stores data in association with a tag defining its location in a main memory, and also includes a buffer for storing a plurality of addresses together with translations of the corresponding main memory locations, permitting data obtained from the auxiliary memory to be validated by comparing the tag with the translation from the buffer. An improvement in the auxiliary memory is disclosed consisting of a content addressable memory (CAM) for storing translations not found in the buffer. The CAM is adapted so that it can be searched for a translation and the translation, if found in the CAM, is employed to verify data in the auxiliary memory.

Abstract: A cursor control system for use with a data terminal having a display consists of a radiation source and associated radiation sensor. Either the source or sensor is fixed with respect to the display while the other is moveable and may be fixed to the user's head. The system translates the motion of the user's head into a directional signal for controlling cursor position on the screen.