Abstract: A scanning display signal generating system for a plurality of planes includes a first look up table addressed by a first set of the planes, and a second look up table addressed by a second set of planes. A logic unit receives the outputs of the tables and provides a display signal which is a selected logical combination of the outputs. A function control unit provides a control signal to the logic unit to select the desired logical combination. A large number of planes are thus displayed using small LUT memory components, providing display values in real time to the scanner. The output of one look up table may be provided as a control signal to the logic unit. In one embodiment the first look up table is addressed by text planes, and an output therefrom provides the control signal for suppressing the output of the second look up table.

Abstract: A high speed switching circuit is disclosed in which two cascode circuits are coupled and operated in push-pull operation. The cascode circuits are clamped to avoid slowing down of the transistors due to saturation.

Abstract: The invention is a debugger which is part of the operating system of a multi-programmable digital data processor with virtual memory. The debugger can identify and correct faults in an embedded operating system of a multi-programmable digital data processor having hardware-controlled process exchange. The debugger is capable of suspending and effectively restarting processes in a primary or second central processing unit, as well as selectively accessing, reading, and/or modifying data at real or virtual memory locations. Further, the debugger can look ahead, using a next instruction prediction function, and determine the location of the next-to-be executed instruction. The debugger can then replace the previous breakpoint with the instruction the break point had originally replaced, and put the breakpoint after the next-to-be executed instruction. The debugger is also capable of simulating the local execution of a replaced instruction and restarting suspended processes.

Abstract: Methods and apparatus for implementing fork operations on UNIX or UNIX-emulating operating systems, particularly in multi-user environments reduce the copy time, the number of page faults and, consequently the input-output ("I/O") operations between the central processing unit, main memory and auxilliary memory. In one aspect of the invention, fork operations are executed by redefining those pages of the parent process image resident in main memory as pages of a child process image and modifying the page maps accordingly. Page faults are thereby eliminated for pages located in auxiliary memory. Additional improvements in performance are obtained by monitoring the level of main memory utilization and selecting optical procedures based on the amount of excess capacity in main memory.

Abstract: A horizontal scrolling apparatus that provides scrolling on a character-by-character basis including a screen memory and associated visual attribute memory having associated therewith a scroll control memory for storing at least one bit for controlling horizontal scrolling. A latch controls writing into the scroll control memory to provide an enable bit therein, only in those locations corresponding to characters that are to be scrolled. An offset number is stored in an offset register, which number is variable under computer control. Operation of an adding circuit is responsive to sensing of the enable bit for adding the offset number to the present screen address to provide an offset address. The offset address is coupled to the video memory for display of the character associated with the offset address in the screen address position.

Abstract: A high frequency power converter circuit having a transformer comprised of a magnetic element having a through hole in combination with a pair of diodes having opposed terminals and at least one of which extends through the magnetic circuit element through hole. Bussbar conductors have the diodes and magnetic element coupled therebetween. The circuit inductance is formed by a further magnetic circuit member associated with one of the bus conductors.

Abstract: A data processing system for processing a sequence of program instructions has a pipeline structure which includes an instruction pipeline and an execution pipeline. Each of the instruction and execution pipelines has a plurality of serially operating stages. The instruction pipeline reads instructions from storage and forms therefrom address data to be employed by the execution pipeline. The execution pipeline receives the address data and uses it for referencing stored data to be employed for execution of the program instructions. A program instruction flow prediction apparatus and method employ a high speed flow prediction storage element for predicting redirection of program flow prior to the time when the instruction has been decoded. Circuitry is further provided for updating the storage element, correcting erroneous branch and/or non-branch predictions, and accommodating instructions occurring on even or odd boundaries of the normally read double word instruction.

Abstract: A bit selection and routing apparatus and method selects m data signals from among its n available data inputs and groups those m signals on its output lines. The apparatus employs a two-dimensional array of signal selection elements which are multiplexing elements. The circuitry is implemented in NMOS technology using pass transistors. The apparatus can be placed in a data flow path and can pass data either unaltered, in a selection mode, in a shift mode, and in a partial data pass mode wherein an upper portion of the input word is set to a predetermined value. The selection elements are connected to route the selected input signals to selected output lines in a predetermined order.

Abstract: A data processing system, wherein the central processing unit has an arithmetic element for processing data in response to machine program instructions and a control store for microcode program storage responsive to the machine instructions for implementing the instruction, has an improved arithmetic unit for enabling higher throughput without substantially increasing hardware cost. The arithmetic unit has a reconfigurable arithmetic logic unit which is controlled in response to both hardware generated data signals and microcode generated data signals. A data string manipulation circuitry provides for aligning data strings for processing by the arithmetic logic unit. Circuitry is provided, responsive to a decoded machine instruction, for generating control signals for configuring the arithmetic unit and for controlling the data string manipulation circuitry.

Abstract: An improved stand-off device is disclosed which is used to control the spacing between adjacent planar elements in electronic instrumentation. The stand-off device includes a resilient, hollow shell member and a rigid, cylindrical inner element. The shell member has at least one slot extending from one end, and has a top interior cylindrical surface, a bottom interior cylindrical surface, and a threaded intermediate interior surface. The inner element has a conical expander portion and a drive portion with a threaded exterior surface which is complementary to the threaded interior intermediate surface of the shell member. The slotted end of the shell member is adapted for insertion into an aperture in a planar member from one side of that member. The inner element is adapted for insertion into the shell member from the same side of that member, whereupon the conical portion forces the slotted end of the shell member to expand and engage the perimeter of the aperture in the planar member.

Abstract: A data processing system for processing a sequence of program instructions has a pipeline structure including an instruction pipeline and an execution pipeline. Each pipeline has a plurality of serially operating stages. The stages read from and modify memory at various stages of instruction processing. Collisions between data read from a register in the instruction pipeline phase of operation in response to a first instruction and write data written into the register during the execution phase of operation in response to an earlier instruction can be detected and predicted. In response thereto, the new data can be substituted directly for the modified data in the pipeline itself to provide continued valid operation. In addition, the apparatus and method provide for altering the flow of the instructions through the pipeline in order to accommodate newly generated data and to avoid invalid operation.

Abstract: An apparatus for controlling visual attributes associated with characters displayed on a video display screen including a video memory for storing multiple data words corresponding to screen character locations, an attribute memory associated with the video memory for storing visual attribute codes and an attribute propagation store associated with the attribute memory for controlling visual attribute code propagation. A latch controls writing into the attribute propagation memory, a control bit for controlling visual attribute code propagation. The apparatus also includes a video display generator and control logic responsive to the control bit for causing a predetermined attribute code to be propagated for a preselected number of screen character locations.

Abstract: A method and apparatus for providing high speed communications with a shared memory from both a processing control unit and a plurality of auxiliary processing devices employs a video random access memory. The processing control unit or units require random access of the memory and are operatively connected to a random access port of the video random access memory. Each auxiliary processing device is operatively connected for data transfer in a burst mode to a serial access port of the video random access memory. The method and apparatus control transfer of data to and from the serial and random access ports for effecting high speed communications at both I/O access ports of the memory. Data communication at the serial access port is in a bit serial/word parallel burst mode and occurs in one CPU cycle. The memory operates like a dynamic RAM from the random access port.

Abstract: A transactional data base processing apparatus which executes plural transactions causing a data base to be updated, incorporates an after-image recovery storage apparatus and method which enables continuous operation of the transaction system. The after-image recovery storage apparatus has a temporary storage file and a permanent storage file with circuitry for writing from the temporary storage file to the permanent storage file. Tha circuitry also writes after-image updating data records to the temporary storage file. The apparatus further includes elements for initiating transfer of the after-image data records from the temporary storage file to the permanent storage prior to a time when the temporary file is filled with the data records. The transfer is accomplished by operating the apparatus on a time shared basis so that other ongoing operations including transactional operations occur as the after-image data is being transferred to a permanent storage device.

Abstract: A size configurable data storage system that comprises a plurality of main storage buffers and a like plurality of input data buffers with the main storage buffers and input data buffers being interconnected by respective data busses. The data storage system is preferably a FIFO (first-in-first-out) system employing random access memories for storage. To accommodate different word width inputs to the input data buffers, there are provided a plurality of inter-bus buffers which individually intercouple between predetermined data busses. There is also provided a controller which includes an inter-bus buffer control circuit for controlling enabling of the inter-bus buffers in predetermined sets to enable at least one thereof when less than the full width of the main storage buffer is being entered. When a full width word is to be stored then all inter-bus buffers are inhibited providing direct data transfer from all input data buffers to the main storage buffers.

Abstract: A memory alignment system and method are disclosed having a memory bus designed to accommodate more than one write instruction at a time and where data from different write instructions are merged together when the writes are destined for alignable locations in memory. In one embodiment, a write buffer and a comparator are configured to compare successive instructions for alignable destination addresses. In another embodiment, a content associative buffer is employed to compare the address of a write instruction with the addresses of all other stored write instructions. A variable scheduler to control the unloading of the buffer is also disclosed as is an apparatus for merging data read from memory with data awaiting transmission to memory to obtain the most up-to-date version.

Abstract: A data processing system for processing a sequence of program instructions has two independent pipelines, an instruction pipeline and an execution pipeline. Each pipeline has a plurality of serially operating stages. The instruction stages read instructions from storage and form therefrom address data to be employed by the execution pipeline. The execution pipeline receives the address data and uses it for referencing stored data to be employed for execution of the program instructions. Both pipelines operate synchronously under the control of a pipeline control unit which initiates operation of at least one stage of the execution pipeline prior to completion of the instruction pipeline for a particular instruction. Thereby operation of at least one instruction stage and one execution stage of the respective pipelines overlap for each program instruction. The instruction and execution pipelines share high speed memory.

Abstract: A cache coherence system for a multiprocessor system including a plurality of data processors coupled to a common main memory. Each of the data processors includes an associated cache memory having storage locations therein corresponding to storage locations in the main memory. The cache coherence system for a data processor includes a cache invalidate table (CIT) memory having internal storage locations corresponding to locations in the cache memory of the data processor. The cache coherence system detects when the contents of storage locations in the cache memories of the one or more of the data processors have been modified in conjuction with the activity those data processors and is responsive to such detections to generate and store in its CIT memory a multiple element linked list defining the locations in the cache memories of the data processors having modified contents.

Abstract: A digital system simulation apparatus and method enable a user to interactively control, during simulation, the sampling of signals in the digital system whose behavior is being simulated. The behavior of the system can be approximated better by recognizing and allowing a precise definition of element outputs even though the element inputs can include undefined variables. The apparatus allows efficient and better utilization of system memories by providing the capability of defining multiple outputs of the circuit elements in a single instruction when those outputs all have common inputs.

Abstract: A method and apparatus for radix-.beta. non-restoring division. The division process occurs in four phases. In a first phase, the input operands are transformed to produce a divisor lying in a designated numerical range. Next, a transitional phase involves generating an initial radix-.beta. quotient digit from the transformed numerator. An iterative phase of the process generates successive partial remainders according to a recursive method. From the sign and a single radix-.beta. digit of each of these partial remainders, the process generates a radix-.beta. quotient digit. Further, a fourth phase, which may run concurrently with the transitional and iterative phases, involves accumulating successively generated quotient digits to produce a final quotient value.