Abstract: A method is achieved for making improved deep trench capacitors for DRAM circuits with reduced trench faceting at the wafer edge and improved pad Si3N4 uniformity for increasing process yields. The method utilizes a thicker pad Si3N4 as part of a hard mask used to etch the deep trenches. Then, after forming the deep trench capacitors by a sequence of process steps a shallow trench isolation (STI) is formed. The method utilizes etching shallow trenches in the same thicker pad Si3N4 layer and into the silicon substrate. A second insulating layer is deposited and polished back (CMP) into the pad Si3N4 layer. A key feature is to use a second mask to protect the substrate center while partially etching back the thicker portion of pad Si3N4 layer at the substrate edge inherently resulting from the CMP. This minimizes the nonuniformity of the pad Si3N4 layer to provide a more reliable structure for further processing.

Abstract: A method of forming an arsenic doped oxide layer in a process chamber is disclosed. The method comprises the steps of: setting the process chamber to a temperature of approximately 400-500° C. and a pressure of about 40-250 torr; flowing tetraethylorthosilicate (TEOS) into the process chamber; flowing triethylarsenate (TEAS or TEASAT) into the process chamber; and flowing ozone into the process chamber.

Abstract: A method for forming a bit line of a DRAM memory array is disclosed. The method comprises the steps of: forming an interlayer dielectric over the DRAM memory array; etching the interlayer dielectric to form trenches in the interlayer dielectric, the trenches collectively forming a bit line pattern and having tapered side walls; and depositing a conductive material into the trenches to form the bit line.

Abstract: A method for forming a metal interconnect having a plurality of metal lines and an interlayer dielectric is disclosed. The metal interconnect has a decreased capacitance between the metal lines of the metal interconnect. First, a metal interconnect is formed onto a substrate. A first HDPCVD oxide layer is formed over the metal interconnect. A second HDPCVD oxide layer is formed over the first HDPCVD oxide layer, the second HDPCVD oxide layer being formed such that air gaps are formed between the metal lines of the metal interconnect. Furthermore, a third HDPCVD oxide layer may be formed over the second HDPCVD oxide layer, the third HDPCVD oxide formed using a sputter to deposition ratio higher than that used to form the second HDPCVD oxide layer.

Abstract: A method of fabricating deep trench capacitors of high density Dynamic Random Access Memory (DRAM) cells is disclosed: first, providing a semiconductor substrate, and then forming a trench on the semiconductor substrate; sequentially forming a capacitor dielectric layer, a first polysilicon storage node, dielectric collars and a second polysilicon stud inside the trench; performing two-step ion implantation to form shallow and deep strap regions on one side of the trench; forming a third polysilicon layer and an isolation layer overlaying the dielectric collars and second polysilicon stud inside the trench to complete a buried strap formation; and forming an access field effect transistor on the semiconductor substrate.

Abstract: An apparatus and method to polish a wafer using abrasive flow machining (AFM) is provided. Under a high-pressure condition, the wafer is polished by flowing abrasive media with high viscosity, on the wafer in order to planarize the wafer. Therefore, the polishing efficiency is higher, and the attained roughness is lower than the conventional method. In addition, the selectivity of this method is lower.

Abstract: An optical mask system for improving the bandwidth in the x-direction of an asymmetrical optical mask, wherein the optical mask has a pattern that varies strongly in the x-direction, but slowly in the y-direction, thus occupying a two-dimensional cigar-shaped area in the transformed Fx-Fy two-dimensional frequency domain. The apparatus and method of the present invention are most advantageous for preparing semiconductor devices whose topography varies strongly in one direction but weakly in another direction. The optical mask system includes: (a) a first diffractive light grating, tilted at a tilting angle &ohgr; relative to an incident light direction, wherein &ohgr; is about 45 degrees; (b) an asymmetric optical mask; (c) a second diffractive light grating, tilted at a tilting angle &phgr; relative to the incident light direction, wherein &phgr; is about 45 degrees; and (d) a low-pass filter.

Abstract: A method and apparatus for filtering a slurry used in a chemical mechanical polishing apparatus is disclosed. Magnets are provided along the piping network between a slurry reservoir and the CMP apparatus. A magnet may also be placed adjacent to the slurry reservoir to prevent iron oxide particles from traveling with the slurry to the CMP apparatus. The magnets attract iron oxide particles from the slurry and remove those particles from the slurry prior to polishing. This reduces the amount of defects caused by the iron oxide particles in the slurry.

Abstract: A method for fabricating deep-submicron vertically arranged capacitors is disclosed which allows the capacitor to enjoy an enhanced sidewall surface so as to attain a capacitance of 40 pF or more.

Abstract: A method for chemical mechanical polishing (CMP) of a wafer having a top layer to be polished is disclosed. The method comprises the steps of: using a CMP apparatus to polish the top layer using a first slurry having abrasive particles of a first size; and using the CMP apparatus to polish the top layer using a second slurry having abrasive particles of a second size, the second size being smaller than the first size.

Abstract: A method for forming the gate electrode in an integrated circuit, in which a cap silicon nitride layer is deposited in a two step process to improve the condition of silicon nitride residue remaining on the surface of tungsten silicide. First, a layer of polysilicon and a layer of tungsten silicide are sequentially formed on the semiconductor substrate, subsequently, a thin film of silicon nitride is formed at a first temperature and a second silicon nitride is formed at a second temperature, then the pattern of the contact window of gate is defined and the first etching is performed to remove the second and the second silicon nitride, finally, the second etching is performed to remove the layers of polysilicon and tungsten silicide to form a gate electrode.

Abstract: A method for making conductive plugs in a semiconductor wafer. In involves the steps of: (a) forming at least one through hole in a dielectric layer, which is formed above a conductive substrate; (b) subjecting the wafer to a NH4OH/H2O2 wet washing process and HCl/H2O2 wet washing process; (c) drying the wafer; (d) subjecting the wafer to a dilute hydrogen fluoride or buffered hydrogen fluoride wet washing process to remove the native oxide layer that maybe formed on the conductive substrate; (e) drying the wafer again; and (i) filling the at least one through hole with a conductive material to form at least one conductive channel. The wet washing station is modified such that the wet washing processes and the drying process are performed in the same station and without removing the wafer from the washing station during the wet washing and drying process.

Abstract: A plasma erosion resistive clamping ring is provided for clamping a wafer in a plasma treatment chamber. The plasma erosion resistive clamping ring comprises a ring and one or more tips secured to, and mutually spaced apart about, a circumference of the ring. Each of the tips projects away from the ring, in a radial direction, towards an interior of the ring. Each tip has plural side surfaces that taper to, and meet, a single, continuous surface of rotation. The surface of rotation is located in the interior of the ring at a location of the tip which is radially most distant from the ring. The meeting of the tapered sides at the single continuous surface of rotation has a cross-section, taken in a plane of the ring, as follows. The cross-section comprises first and second line segments, on lines that intersect at an acute angle, and an arc of a convex ellipse, that begins at an end of the first line segment most distant from the ring, and ends at an end of the second line segment most distant from the ring.

Abstract: A method of forming the gate structure of a MOS device forms a gate structure over a semiconductor substrate and then treats the sidewalls of the gate structure with nitrous oxide plasma so that the silicon and tungsten atoms within the gate structure can react with activated nitrogen in the plasma to form chemical bonds. Hence, a protective layer is formed on the gate sidewalls, thereby increasing thermal stability of the tungsten suicide layer and the polysilicon layer within the gate structure. Thereafter, an oxide material is formed over the protective layer using a rapid thermal oxidation. Next, spacers are formed over the sidewall oxide layer. Finally, subsequent operations necessary for forming a complete MOS device are performed.

Abstract: A method of fabricating a semiconductor device is provided including the steps of:(a) forming one or more protrusions on a semiconductor surface,(b) forming a first O.sub.x /TEOS film on top and side surfaces of the protrusions and surface area portions of the semiconductor surface separating the protrusions from each other, if any, and(c) forming a second O.sub.3 /TEOS film on, and covering, the first film.Illustratively, the protrusions have nitride regions at their peaks. The first film can be a low pressure (e.g., 30-70 torr) O.sub.3 /TEOS film or a plasma enhanced chemical vapor deposition (PECVD) O.sub.2 /TEOS film. The second film is a high pressure (e.g., 200-600 torr) O.sub.3 /TEOS film.The high pressure O.sub.3 /TEOS film avoids all of the disadvantages of the prior art. The low pressure O.sub.3 /TEOS film or PECVD O.sub.2 /TEOS film covers the nitride region of the protrusion so that the high pressure O.sub.3 /TEOS film will continuously cover the entire structure with a uniform thickness.

Abstract: A method of forming a thermally stable tungsten silicide layer. The method includes sequentially forming a polysilicon layer and a tungsten silicide layer over a semiconductor substrate. Then, the semiconductor substrate is exposed to nitrogen (N.sub.2) plasma at room temperature so that a nitridation reaction can be initiated, thereby forming a thin tungsten nitride layer over the tungsten silicide layer. Thereafter, a silicon nitride layer is formed over the tungsten nitride layer. Since the thermal stability of a tungsten nitride layer is higher, the probability of re-crystallization in the tungsten silicide layer when the silicon nitride layer is subsequently deposited is reduced. Moreover, tungsten nitride is able to fill the voids and crevices at the grain boundaries of the tungsten silicide layer after the tungsten silicide layer is re-crystallized. Finally, photolithographic and etching operations are carried out to form a gate structure over the semiconductor substrate.

Abstract: A method of forming metal lines is disclosed. The method comprises the steps of: forming a composite metal layer over a wafer, the composite metal layer having a top layer of titanium/titanium nitride; oxidizing the top layer of titanium/titanium nitride to form a layer of titanium oxide; and patterning and etching the composite metal layer to form the metal lines.

Abstract: A method of reducing agglomerated particles in a slurry for use in a chemical mechanical polishing (CMP) machine, the CMP machine also using deionized water, is disclosed. The method comprises the steps of: monitoring the pH of the slurry that is provided to the CMP machine; monitoring the pH of the deionized water that is provided to the CMP machine; and adjusting the pH of the deionized water to be substantially the same as the pH of the slurry.

Abstract: A method for improving etch uniformity during a wet etching process is disclosed. The method comprises the steps of first rinsing the wafer to form a water film over the wafer surface, followed by liquid phase etching. The water film helps the subsequent viscous etchant to be spread across the wafer surface more uniformly to thereby improve the etch uniformity.

Abstract: A clamp affixes a wafer by entirely covering the edge of the wafer, wherein the radius of the inner surface of the clamp is about 1 mm shorter than the radius of the wafer. Besides, there are four pairs of square protuberances distributed even along the inner surface of the clamp for affixing the wafer, wherein the square protuberances only hold the edge of the device regions of the wafer. Even though the wafer is slightly off position, the square protuberances are still able to affix the wafer properly. In addition, the lifetime of the clamp of the invention is about 100 hours, which is two times of a conventional clamp, so that the cost is reduced.