Abstract: An apparatus for identifying state dependent defect related leakage currents in a tested circuit with a defect. The apparatus includes a test system providing an input signal and an operating voltage, and a reference circuit the same as the tested circuit but without the defect receiving the input signal and the operating voltage, and operating at a first operating current, wherein, the tested circuit also receives the input signal and the operating voltage, and operates at a second operating current, and the test system senses a difference of the first and second operating current.

Abstract: A method for manufacturing a semiconductor device includes providing a dielectric layer over a substrate, providing a first photoresist layer over the dielectric layer, patterning and defining the first photoresist layer, etching the first photoresist layer and the dielectric layer to form a plurality of vertical openings, removing the first photoresist layer, depositing a second photoresist layer over the dielectric layer, wherein the second photoresist layer fills the plurality of vertical openings, removing only a portion of the second photoresist layer deposited over the dielectric layer, wherein the second photoresist layer has a first substantially uniform thickness over the dielectric layer, depositing an anti-reflection coating layer over the second photoresist layer, providing a third photoresist layer over the anti-reflection coating layer, patterning and defining the third photoresist layer, and etching the anti-reflection coating layer and the second photoresist layer to form a plurality of trench

Abstract: A memory device that includes a semiconductor substrate, and an array of memory cells, each cell being electrically isolated from adjacent cells and including an island formed from the substrate, the island having a top portion and at least one sidewall portion, and being spaced apart from other islands by a bottom surface on the substrate, a capacitor formed contiguous with the sidewall portion, and a transistor formed on the top portion of the island, the transistor including a gate oxide layer formed on a surface of the top portion, a gate formed on the gate oxide layer, and a first and a second diffused regions formed in the top portion, the first diffused region being spaced apart from the second diffused region.

Abstract: An opening through an insulating layer between a first layer and a second layer of a semiconductor device is formed where the second layer is a polysilicon or amorphous silicon hard mask layer. The polysilicon or amorphous silicon hard mask layer is etched to form at least one opening through the polysilicon or amorphous silicon hard mask layer using a patterning layer as a mask having at least one opening. The insulating layer is etched to form the opening through the insulating layer using the etched polysilicon or amorphous silicon hard mask layer as a mask. The etched polysilicon or amorphous silicon hard mask layer is nitridized prior to subsequent processing.

Abstract: A method of forming capacitor dielectric structure, comprising steps of providing a semiconductor substrate having at least a predetermined capacitor structure, using silicon nitride deposition to form a SiN layer on the predetermined capacitor structure, using a reoxidation process to grow an oxide layer on the SiN layer, and using a nitridation process to form a nitridation layer on the oxide layer.

Abstract: A method for avoiding defects produced in The CMP process has the following steps: sequentially depositing a first dielectric layer and a second dielectric layer on a semiconductor substrate, wherein the wet-etching rate of the first dielectric layer is greater than the wet-etching rate of the second dielectric layer; forming a plurality of first holes on a plurality of the predetermined contact window areas respectively; wet etching the first dielectric layer in each of the first holes to form a plurality of second holes on the plurality of the predetermined contact window areas respectively; forming a conductive layer to fill each of the second holes; and performing the CMP process to level off the conductive layer and the second dielectric layer.

Abstract: A method for measuring a bias voltage of plural sense amplifiers in a memory device is provided. The method includes the steps of: selecting the plural sense amplifiers as a measurement area, writing a midlevel voltage into the respective memory cell modules connected to the plural the sense amplifiers respectively, providing a reference voltage of the midlevel voltage into the plural sense amplifiers in the measurement area, recording output signals of the plural sense amplifiers, wherein the output signal is valued one of “0” and “1”, counting numbers of “0” and “1”, and obtaining a ratio of the number of “0” over the number of “1”, and obtaining the bias voltage of the plural sense amplifiers in the measurement area as the ratio.

Abstract: A method of increasing DRAM cell capacitance via formation of deep, wide diameter trench capacitor structures, has been developed. An underlying semiconductor substrate is used to accommodate deep, wide diameter trench capacitor structures while an overlying, bonded, thinned semiconductor substrate is used to accommodate narrow diameter trench structures, in turn used for communication to the underlying deep trench capacitor structures, as well as to accommodate the elements of the DRAM device, such as the transfer gate transistors. The use of an underlying semiconductor substrate for accommodation of the trench capacitor structures allows a wider diameter structures to be used, thus reducing patterning difficulties encountered when forming narrow diameter, deep trench capacitor structures.

Abstract: The present invention provides a metal contact of SiGe combined with cobalt silicide and cobalt. The contact resistance is greatly lowered due to both the low Schottky Barrier Height of SiGe and the low sheet resistance of cobalt silicide. The cobalt layer can serve as a glue layer and diffusion barrier layer. Thus, no additional glue layer or diffusion barrier layer needs to be formed. Moreover, the metal contact of the present invention can be integrated with a DRAM by a hybrid contact method. Implantation contact is used in pFET regions and diffusion contact is used in nFET regions. This can reduce mask steps and production costs.

Abstract: The present invention provides a semiconductor device in which a low resistance, tunable contact is formed by means of using a SixGe1−x (0<x<1) layer. Thus, only moderate doping is required, which in turn protects the device from short channel effect and leakage. The low resistance, tunable contact is suitable for CMOS devices.

Abstract: An improved buried strap method in the fabrication of a DRAM integrated circuit device is described. A deep trench is etched into a substrate. A collar is formed on an upper portion of the deep trench. A buried plate is formed by doping around a lower portion of the deep trench and a capacitor dielectric layer is formed within the deep trench. The deep trench is filled with a silicon layer wherein the silicon layer forms a deep trench capacitor and covers the collar. The silicon layer is recessed below a top surface of the substrate to leave a recess. A top portion of the collar is etched away to leave a collar divot. A hemispherical grain polysilicon layer is selectively deposited into the deep trench and filling the collar divot. The HSG layer is doped in-situ or by post plasma doping. The doped hemispherical grain polysilicon layer forms a buried strap in the fabrication of a deep trench DRAM integrated circuit device.

Abstract: The present invention provides a semiconductor device for detecting gate defects and the method of using the same to detect gate defects. The semiconductor device is comprised of a semiconductor substrate having an oxide layer on the top, a gate having spacers, formed on the oxide layer and surrounding the semiconductor substrate, wherein the gate is also patterned to divide the semiconductor substrate into two parts not electrically connected, and a conductive layer formed on the semiconductor outside the gate. In addition, the method for using the semiconductor device of the present invention to detect gate defects is comprised of applying a ground voltage and a set voltage respectively to two parts divided by the gate in the semiconductor device, and measuring current between the two parts.

Abstract: The invention provides an apparatus for identifying state dependent defect related leakage currents in a tested circuit with a defect. The apparatus comprises a test system providing an input signal and an operating voltage, and a reference circuit the same as the tested circuit but without the defect receiving the input signal and the operating voltage, and operating at a first operating current, wherein, the tested circuit also receives the input signal and the operating voltage, and operates at a second operating current, and the test system senses a difference of the first and second operating current.

Abstract: A consolidated junction contact etch in the fabrication of a DRAM integrated circuit device is described. Semiconductor device structures are provided in and on a substrate wherein the substrate is divided into an active area and a periphery area. The semiconductor device structures are covered with an etch stop layer. A dielectric layer is deposited over the etch stop layer. The dielectric layer is concurrently etched through in the active area to form bit line contact openings, in the periphery area to form substrate contact openings, and to form gate contact openings wherein the etching stops at the etch stop layer. The etch stop layer is etched into to a lesser extent through the substrate contact openings and the bit line contact openings than through the gate contact openings. Then, the etch stop layer is etched through using a directional etch selective to the etch stop layer.

Abstract: A method of forming a buried strap comprising the following sequential steps. A substrate having a pad oxide layer formed thereover is provided. A masking layer is formed over the pad oxide layer. The masking layer, pad oxide layer and substrate are etched to form a trench within the substrate. The trench having an outer sidewall and an upper portion. The upper portion of the trench is lined with a collar. A poly plate is formed within the trench. The poly plate and collar are etched below the substrate to form a recessed poly plate and a recessed collar and exposing a portion of outer sidewall of trench. Ions are implanted into the substrate through exposed outer sidewall of trench by gas phase doping. A SiN sidewall layer is formed over the exposed outer sidewall of trench at a temperature sufficient to diffuse the implanted ions further into the substrate to form the buried strap.

Abstract: A method is disclosed to determine and assess chamber inconsistency in a multi-chambered tool, especially a multi-chambered tool involved in mass production processes. Wafers produced by the tool are grouped in lots measured to obtain loss yield groups. The invention sorts yield losses to obtain a corresponding monotonic sequence. The invention then averages the monotonic sequences. If the resulting mean monotonic sequence fits with a predetermined aberration, the tool is determined to suffer from chamber inconsistency.

Abstract: The present invention provides an inline detection device for self-aligned contact defects, formed in a semiconductor substrate, comprising: an active area, formed in the semiconductor substrate, comprised of a first gate having spacers on the side, at least one contact window formed between the spacers, a first contact plug formed in the first contact window, and a first contact area connecting with the first contact plug; and at least two probing pads, formed in the semiconductor substrate, comprised of a plurality of second gates formed with spacers on the side, second contact windows exposing the second gates, a second contact plug formed in the second contact window, and a second contact area connecting with the first contact area. According to the present invention, defects are detected by electrical measurement immediately following the formation of contact plugs.

Abstract: The present invention provides a metal contact of SiGe combined with cobalt silicide and cobalt. The contact resistance is greatly lowered due to both the low Schottky Barrier Height of SiGe and the low sheet resistance of cobalt silicide. The cobalt layer can serve as a glue layer and diffusion barrier layer. Thus, no additional glue layer or diffusion barrier layer needs to be formed. Moreover, the metal contact of the present invention can be integrated with a DRAM by a hybrid contact method. Implantation contact is used in pFET regions and diffusion contact is used in nFET regions. This can reduce mask steps and production costs.

Abstract: A new method to reduce variation in an output parameter by selection of an optimal process recipe in the manufacture of an integrated circuit device is achieved. The method may be used to reduce the array voltage threshold in a DRAM circuit by compensating the source/drain ion implantation by calculating a predicted array voltage threshold. The integrated circuit device wafer is measured to obtain a present set of process parameter values. A predicted value of an output parameter is calculated by evaluating a first equation at the present set of process parameter values. The first equation is derived from a plurality of previous sets of process parameter values and the corresponding plurality of sets of output parameter values. The difference between the predicted value of the output parameter and a target value of the output parameter is the output parameter delta. A process recipe offset is calculated by evaluating a second equation at the output parameter delta.

Abstract: A new method of forming gate conductor lines for a DRAM in the manufacture of an integrated circuit device has been achieved. A semiconductor substrate is provided. Active areas are defined. A gate conductor layer is deposited overlying the semiconductor substrate. The gate conductor layer is patterned to form gate conductor lines. The intersections of the gate conductor lines and the active areas form DRAM transistors. Adjacent gate conductor lines are spaced a first minimum distance in critical regions and are spaced a second minimum distance in non-critical regions. The critical regions are defined as the active areas between adjacent gate conductor lines where bit line contacts are planned. The non-critical regions are defined as areas located between the critical regions and the adjacent gate conductor lines. The second minimum distance is greater than the first minimum distance to thereby decrease the aspect ratio in the non-critical regions to less than the aspect ratio in the critical regions.