Abstract: Aspects for increasing yield in an embedded memory device are described. With the aspects of the present invention, a cache is provided for a memory unit of an embedded memory device. Attempts to access a failed bit memory location in the memory unit are determined. When a failed memory bit location is being accessed, substitution of a memory location in the cache for the failed bit memory location occurs.

Abstract: A profile control system for controlling a profile of a polishing pad, adapted in a chemical mechanical polishing (CMP) apparatus comprises: a polishing pad, a polishing table, a polishing head, and a conditioner, wherein the polishing pad has a transparent region. The control system includes at least one illuminant, a detector and a processor. The illuminant is in the polishing table and corresponds to the transparent region of the polishing pad. The detector is over the polishing pad to detect the light from the illuminant passing through the transparent region of the polishing pad. The processor is adapted to determine the thickness of the polishing pad according to the light detected by the detector and transmits a processing signal to the conditioner for adjusting processing recipes of the conditioner. Therefore, it is possible to obtain a polishing pad of a desired profile and the variations of the uniformity of the wafers can be reduced.

Abstract: A trench capacitor process for preventing parasitic leakage. The process is capable of blocking leakage current from a parasitic transistor adjacent to the trench, and includes the steps of forming a doping layer and a cap layer covering portions of the sidewall of the trench and performing an annealing process on the doping layer to form a dopant region in the substrate adjacent to each sidewall of the trench and blocks leakage current from a parasitic transistor adjacent to the trench.

Abstract: A latch circuit and method of operation improves the performance of an integrated circuit memory by adding an extra latch into the write data path. The added latch is programmable such that it either is disabled (allowing the transparent flow of data), or enabled (data flow is inhibited by extra clock). In areas of the chip where the address/control information is fast, but the data is slow, the latch is disabled to allow the data to flow as fast as possible. In areas of the chip where the address/control information is slow, but the data is fast, the latch is enabled such that data cannot flow freely and must be gated by clock information.

Abstract: The present invention discloses method and apparatus for wafer analysis. First, a plurality of specific distribution maps, which respectively refer to a defect pattern distribution in a pattern group, is defined. Next, a plurality of distribution features is defined so that each specific distribution map correlates to one of the distribution features. Then, each pattern group on the wafer is compared to each specific distribution map in order to relate each pattern group to at least one of the specific distribution maps, and relate each pattern group on the wafer indirectly to at least one of the distribution features while allocating each distribution feature indirectly related to each pattern group with a respective relative value. Finally, the relative values of each distribution feature are totaled on the wafer respectively to obtain total values of the distribution features.

Abstract: A pre-biased voltage level shifting circuit of especial applicability with respect to those integrated circuit devices requiring a technique for converting circuit operation between differing power supply levels. In a representative embodiment, the circuit utilizes feedback to make the switching transistors faster to thereby increase the speeds of the level translation of signals based upon two different power supplies.

Abstract: A method for forming oxynitride layer. The method includes (a) providing a substrate and removing the native oxide layer; (b) forming a nitride layer on the substrate; (c) oxidizing the nitride layer to form an oxynitride layer; and (d) subjecting the oxynitride layer to in-situ annealing. This method inhibits the penetration of boron into the substrate thereby improving the performance of semiconductor devices and production yield.

Abstract: A method for manufacturing a semiconductor device that includes providing a first layer, cleaning the first layer, growing an oxide layer over the first layer at a reduced pressure from an atmospheric pressure, and depositing a nitride layer over the oxide layer, wherein the growing of the oxide layer and depositing of the nitride layer are performed in the same furnace.

Abstract: A chemical mechanical polishing (CMP) apparatus with temperature control. The apparatus controls circular zone temperature of the wafer. The CMP apparatus comprises a platen; a carrier holding a wafer against the platen; a guide ring disposed at the rim of the carrier to mount the wafer on the carrier; and a heater disposed in the guide ring, in the carrier, or used to heat the slurry. The temperature of the heater is set between 20° C. and 60° C. Thus, the polishing rate at the edge is improved, and the polishing difference between the edge and the center of the wafer is reduced.

Abstract: A method for generating a center error signal in an optical storage system, as well as an optical storage system, is disclosed. Through the use of the method and system in accordance with the present invention, a decrease in manufacturing costs is achieved since very precise and expensive mirrors and/or photo detectors are not needed. A first embodiment of the invention includes a method for generating a center error signal in an optical storage system, the optical storage system comprising a tracking coil and an optical pick up unit, the optical pick up unit including a light beam. The method comprises the steps of sensing a voltage by a tracking coil, providing the voltage to a center error generation circuit, generating a center error signal from the center error generation circuit based on the voltage and utilizing the center error signal to center the light beam. A second embodiment of the invention includes an optical storage system.

Abstract: A method for manufacturing a semiconductor device that includes providing a substrate, providing a dielectric layer over the substrate, depositing a layer of anti-reflective coating over the dielectric layer, providing a layer of photoresist over the layer of anti-reflective coating, patterning and defining the photoresist layer to provide a plurality of photoresist structures, wherein at least two adjacent photoresist structures provide a first distance, anisotropically etching the layer of anti-reflective coating unmasked by the photoresist structures to remove only a portion of the anti-reflective coating layer, etching the anti-reflective coating to completely remove the layer of anti-reflective coating unmasked by the photoresist structures, and etching the dielectric layer to form at least one trench between the at least two adjacent photoresist structures, wherein the first distance is substantially equal to a second distance defining an opening at the top of the trench.

Abstract: A multi-bank memory array architecture utilizing topologically non-uniform blocks of sub-arrays and input/output (“I/O”) assignments in an integrated circuit memory device. By using non-uniform blocks of multiple identical sub-arrays, non-uniform assignments of blocks to banks and/or non-uniform assignments of I/Os to blocks, it is possible to optimize the dimensions of the chip and the placement of the I/Os with respect to the package pads. In this manner, the granularity of the building blocks of sub-arrays is improved while the flexibility in I/O assignment is also improved leading to more efficient and flexible chip layouts.

Abstract: A method of improving uniformity control in chemical mechanical polishing (CMP). A CMP apparatus is provided with at least a platen, a polishing pad disposed on the platen and at least a polishing carrier installed over the platen. The platen rotates in a first rotating direction, and the polishing carrier is used to press a wafer on the polishing pad and drive the wafer to rotate. First, in a first-CMP step, the polishing carrier rotates in a second rotating direction. Then, in a second-CMP step, the polishing carrier rotates in a third rotating direction different from the second rotating direction.

Abstract: A method of forming a deep trench DRAM cell on a semiconductor substrate has steps of: forming a deep trench capacitor in the semiconductor substrate; using silicon-on-insulator (SOI) technology to form a silicon layer on the deep trench capacitor; and forming a vertical transistor on the silicon layer over the deep trench capacitor, wherein the vertical transistor is electrically connected to the deep trench capacitor.

Abstract: The present invention provides a method and system for error correction in optical media data processing. The method includes demodulating a data using a conversion table; marking errors which occur during the demodulation; utilizing estimated values for the marked errors; and performing error correction. The method and system marks errors which occur during demodulation. A logic array is used to obtain estimated values for the marked errors. The marking of errors and the use of values from the logic array for the marked errors increases the probability of the C1 and C2 correction processes being able to correct the errors. Fewer “not correctable” data results. This increases the integrity of the read data.

Abstract: A time data compression technique which allows high speed integrated circuit (“IC”) memory devices to be tested at full speed with test equipment which is capable of operating at only at relatively slower speeds than that of the memory devices without increasing test time or decreasing production throughput. Through the use of the technique disclosed herein, data is initially sorted in time and them compared for a predetermined number of logic level “1s” or “0s” to be effectively compressed in time. This time compression allows high rate data streams to be tested at effectively slower rates. The technique of the present invention can be utilized to effectively reduce the data rate by one half, one quarter or to any sub-multiple of the normal memory frequency without increasing time in test.

Abstract: The present invention provides a method for signal vibration alert. The method of the present invention recognizes significant substantial swerves and corresponding substantial edge-to-edge differences by eliminating the adverse effect of noise among signals generated by an apparatus. When the frequency of the substantial edge-to-edge differences that exceed an acceptable range of the frequency limit is too large, the method of the present invention automatically generates an alert to indicate aberration in the apparatus such that the monitoring staff is informed and allowed to take necessary measures responding to the aberration.

Abstract: A method for manufacturing a semiconductor device includes providing a dielectric layer over a substrate, providing a first photoresist layer over the dielectric layer, patterning and defining the first photoresist layer, etching the first photoresist layer and the dielectric layer to form a plurality of vertical openings, removing the first photoresist layer, depositing a second photoresist layer over the dielectric layer, wherein the second photoresist layer fills the plurality of vertical openings, removing only a portion of the second photoresist layer deposited over the dielectric layer, wherein the second photoresist layer has a first substantially uniform thickness over the dielectric layer, depositing an anti-reflection coating layer over the second photoresist layer, providing a third photoresist layer over the anti-reflection coating layer, patterning and defining the third photoresist layer, and etching the anti-reflection coating layer and the second photoresist layer to form a plurality of trench

Abstract: The present invention provides a metal contact of SiGe combined with cobalt silicide and cobalt. The contact resistance is greatly lowered due to both the low Schottky Barrier Height of SiGe and the low sheet resistance of cobalt silicide. The cobalt layer can serve as a glue layer and diffusion barrier layer. Thus, no additional glue layer or diffusion barrier layer needs to be formed. Moreover, the metal contact of the present invention can be integrated with a DRAM by a hybrid contact method. Implantation contact is used in pFET regions and diffusion contact is used in nFET regions. This can reduce mask steps and production costs.

Abstract: A system and method for finding a defective tool in a semiconductor fabrication facility is disclosed. When the tools process the wafers, data representing the time period during which each wafer passes through each tool is sent to a database. The wafers are tested for defects, and lots having wafers with common failure signatures are determined. A lot list for each tool is generated, a positive weight value is assigned to each bad lot, and a negative weight value is assigned to each good lot. A cumulative value is calculated for each tool by sequentially adding the weight values of each lot in the lot list and keeping the cumulative value above or equal to zero. The tool with the largest maximum cumulative value is the tool that is most likely to be defective.