Abstract: The present invention provides improved MEMS devices and methods for use with fiber-optic communications systems. In one embodiment, an apparatus (100) for steering light has a base layer (110), a beam layer (114) and a folded flexure assembly (120) coupled therebetween. The folded flexure assembly complete underlies the beam layer, and facilitates rotation of the beam layer relative to the base layer. The flexure assemblies further provide a counter rotation force to help prevent the beam layer from sticking in an actuated position. In one aspect, the base layer includes raised portions (140, 142) which operate as mechanical stops for the beam layer. In this manner, the counter rotation force helps prevent the beam layer from sticking to the base layer or the raised portions.

Abstract: An array processor includes processing elements (00, 01, 02, 03, 10, 11, 12, 13, 20, 21, 22, 23, 30, 31, 32, 33) arranged in clusters (e.g., 44, 46, 48, 50) to form a rectangular array (40). Inter-cluster communication paths (88) are mutually exclusive. Due to the mutual exclusivity of the data paths, communications between the processing elements of each cluster may be combined in a single inter-cluster path, thus eliminating half the wiring required for the path. The length of the longest communication path is not directly determined by the overall dimension of the array, as in conventional torus arrays. Rather, the longest communications path is limited by the inter-cluster spacing. Transpose elements of an N×N torus may be combined in clusters and communicate with one another through intra-cluster communications paths. Transpose operation latency is eliminated in this approach. Each PE may have a single transmit port (35) and a single receive port (37).

Abstract: A method and apparatus are provided for spectral grooming of light having a multiple spectral bands. The light is received at an input port and encounters an optical train disposed between the input port and at least one output port. The optical train provides optical paths for routing the spectral bands and includes a dispersive element disposed to intercept light traveling from the input port. An attenuation mechanism is provided for independently attenuating the individual spectral bands. The attenuation mechanism has multiple configurable attenuation elements disposed so that each spectral band is attenuated in accordance with a state of one of the configurable attenuation elements.

Abstract: A variety of advantageous mechanisms for improved data transfer control within a data processing system are described. A DMA controller is described which is implemented as a multiprocessing transfer engine supporting multiple transfer controllers which may work independently or in cooperation to carry out data transfers, with each transfer controller acting as an autonomous processor, fetching and dispatching DMA instructions to multiple execution units. In particular, mechanisms for initiating and controlling the sequence of data transfers are provided, as are processes for autonomously fetching DMA instructions which are decoded sequentially but executed in parallel.

Abstract: Mapping circuitry (40) comprises a first candidate output value producing unit (42) which produces a first candidate output value (C1) that differs by a first offset value (x) from a received input value (r). A second candidate output value producing unit (44) operates, during operation of the first candidate output value producing unit (42) to produce the first candidate output value (C1), to produce a second candidate output value (C2) that differs by a second offset value (y) from the received input value (r). The first and second offset values (x, y) are such that a difference between them is equal to a difference between respective output-range limit values defining the limits of a preselected range of allowable values, and such that, for any input value (r) within a preselected range of allowable input values, one of the first and second candidate output values (C1, C2) is within the preselected output-value range and the other of those two values is outside that range.

Abstract: An image segmenter uses one or more techniques to accurately segment an image, including the use of a progressive flood fill to fill incompletely bounded segments, the use of a plurality of scaled transformations and guiding segmentation at one scale with segmentation results from another scale, detecting edges using a composite image that is a composite of multiple color planes, generating edge chains using multiple classes of edge pixels, generating edge chains using the plurality of scaled transformations, and/or filtering spurious edges at one scale based on edges detected at another scale.

Abstract: A microstructure for steering light is provided that mitigates stiction. A substrate is provided on which a structural linkage is connected to support a structural film. The structural film includes a reflective coating. A hold electrode is connected with the substrate at a position laterally beyond an orthogonal projection of the structural film on the substrate. It is configured to hold the structural film electrostatically in a tilted position with respect to the substrate upon application of a potential difference between the structural film and the hold electrode. Because of its positioning with respect to the structural film, it is ensured that the structural film is not in contact with the substrate when the structural film is being held by the hold electrode.

Abstract: A ManArray processor pipeline design addresses an indirect VLIW memory access problem without increasing branch latency by providing a dynamically reconfigurable instruction pipeline for SIWs requiring a VLIW to be fetched. By introducing an additional cycle in the pipeline only when a VLIW fetch is required, the present invention solves the VLIW memory access problem. The pipeline stays in an expanded state, in general, until a branch type or load VLIW memory type operation is detected returning the pipeline to a compressed pipeline operation. By compressing the pipeline when a branch type operation is detected, the need for an additional cycle for the branch operation is avoided. Consequently, the shorter compressed pipeline provides more efficient performance for branch intensive control code as compared to a fixed pipeline with an expanded number of pipeline stages.

Abstract: The ManArray core indirect VLIW processor consists of an array controller sequence processor (SP) merged with a processing element (PE0) closely coupling the SP with the PE array and providing the capability to share execution units between the SP and PE0. Consequently, in the merged SP/PE0 a single set of execution units are coupled with two independent register files. To make efficient use of the SP and PE resources, the ManArray architecture specifies a bit in the instruction format, the S/P-bit, to differentiate SP instructions from PE instructions. Multiple register contexts are obtained in the ManArray processor by controlling how the array S/P-bit in the ManArray instruction format is used in conjunction with a context switch bit (CSB) for the context selection of the PE register file or the SP register file.

Abstract: A highly parallel data processing system includes an array of n processing elements (PEs) and a controller sequence processor (SP) wherein at least one PE is combined with the controller SP to create a Dynamic Merged Processor (DP) which supports two modes of operation. In its first mode of operation, the DP acts as one of the PEs in the array and participates in the execution of single-instruction-multiple-data (SIMD) instructions. In the second mode of operation, the DP acts as the controlling element for the array of PEs and executes non-array instructions. To support these two modes of operation, the DP includes a plurality of execution units and two general-purpose register files. The execution units are “shared” in that they can execute instructions in either mode of operation. With very long instruction word (VLIW) capability, both modes of operation can be in effect on a cycle by cycle basis for every VLIW executed.

Abstract: A manifold array topology includes processing elements, nodes, memories or the like arranged in clusters. Clusters are connected by cluster switch arrangements which advantageously allow changes of organization without physical rearrangement of processing elements. A significant reduction in the typical number of interconnections for preexisting arrays is also achieved. Fast, efficient and cost effective processing and communication result with the added benefit of ready scalability.

Abstract: A wavelength router that selectively directs spectral bands between an input port and a set of output ports. The router includes a free-space optical train disposed between the input ports and said output ports, and a routing mechanism. The free-space optical train can include air-spaced elements or can be of generally monolithic construction. The optical train includes a dispersive element such as a diffraction grating, and is configured so that the light from the input port encounters the dispersive element twice before reaching any of the output ports. The routing mechanism includes one or more routing elements and cooperates with the other elements in the optical train to provide optical paths that couple desired subsets of the spectral bands to desired output ports. The routing elements are disposed to intercept the different spectral bands after they have been spatially separated by their first encounter with the dispersive element.

Abstract: A wavelength router that selectively directs spectral bands between an input port and a set of output ports. The router includes a free-space optical train disposed between the input ports and said output ports, and a routing mechanism. The free-space optical train can include air-spaced elements or can be of generally monolithic construction. The optical train includes a dispersive element such as a diffraction grating, and is configured so that the light from the input port encounters the dispersive element twice before reaching any of the output ports. The routing mechanism includes one or more routing elements and cooperates with the other elements in the optical train to provide optical paths that couple desired subsets of the spectral bands to desired output ports. The routing elements are disposed to intercept the different spectral bands after they have been spatially separated by their first encounter with the dispersive element.

Abstract: An optical arrangement and method are provided for receiving a light beam having a plurality of spectral bands and directing subsets of the spectral bands along optical paths to respective optical elements. The light beam is received at an input port. The optical elements which route the spectral bands are configured as a substantially planar array. A dispersive element is configured to angularly spread the light beam, after it has been collimated, into a plurality of angularly separated beams that correspond to the plurality of spectral bands. A first focusing element is disposed with respect to the dispersive element and with respect to the array of optical elements such that variation of focal length with wavelength of the separated beams is compensated by the field curvature of the optical system, and the final image surface is flattened.

Abstract: General purpose flags (ACFs) are defined and encoded utilizing a hierarchical one-, two- or three-bit encoding. Each added bit provides a superset of the previous functionality. With condition combination, a sequential series of conditional branches based on complex conditions may be avoided and complex conditions can then be used for conditional execution. ACF generation and use can be specified by the programmer. By varying the number of flags affected, conditional operation parallelism can be widely varied, for example, from mono-processing to octal-processing in VLIW execution, and across an array of processing elements (PE)s. Multiple PEs can generate condition information at the same time with the programmer being able to specify a conditional execution in one processor based upon a condition generated in a different processor using the communications interface between the processing elements to transfer the conditions.

Abstract: An improved optical power transient control scheme is provided for optical amplifiers used in long haul, high capacity DWDM optical networks. The optical power transient control scheme employs a combination of feed-forward and feedback control mechanisms to adjust the pump laser current of an amplifier. In this way, the optical power transient control scheme allows for very fast detection of transient changes in optical input power and fast control settling time with minimal optical power degradation.

Abstract: Scheduling is performed for a switch fabric (e.g., an input-buffered switch fabric). A first input port from a set of input ports is selected, for a first output port, based on a weight value uniquely associated with each link from a first set of links. Each link from the first set of links are between the first output port and a unique input port from the set of input ports. A second output port from a set of output ports is selected for a second input port.

Abstract: Mapping circuitry (40) comprises a first candidate output value producing unit (42) which produces a first candidate output value (C1) that differs by a first offset value (x) from a received input value (r). During operation of the first candidate output value producing unit (42) a second candidate output value producing unit (44) produces a second candidate output value (C2) that differs by a second offset value (y) from the received input value (r). One of the first and second candidate output values is within a preselected range of allowable output values and the other is outside that range. An in-range value determining unit (46) determines which one of the first and second candidate output values is within the range, and an output value selection unit (48) selects this value as the output value (p) corresponding to the received input value (r).

Abstract: Many video processing applications, such as the decoding and encoding standards promulgated by the moving picture experts group (MPEG), are time constrained applications with multiple complex compute intensive algorithms such as the two-dimensional 8×8 IDCT. In addition, for encoding applications, cost, performance, and programming flexibility for algorithm optimizations are important design requirements. Consequently, it is of great advantage to meeting performance requirements to have a programmable processor that can achieve extremely high performance on the 2D 8×8 IDCT function. The ManArray 2×2 processor is able to process the 2D 8×8 IDCT in 34-cycles and meet the IEEE standard 1180-1990 for precision of the IDCT. A unique distributed 2D 8×8 IDCT process is presented along with the unique data placement supporting the high performance algorithm.

Abstract: A number of methods and systems for overcoming stiction are provided. The systems include electromechanical systems capable of exerting a variety of forces upon areas prone to stiction. The systems can be MEMS arrays or other types of devices where stiction related forces occur. The methods include a variety of ways of causing movement in areas prone to stiction forces. Such movement can be vibrational in nature and is sufficient to overcome stiction, allowing a trapped element to be moveed to a desired location.