Abstract: A tunable demultiplexer accepts an input optical signal that has multiple spectral bands and provides multiple output signals. Each of the output signals corresponds to a selected one of the spectral bands. The tunable demultiplexer has at least one wavelength routing element and at least one optical arrangement disposed to exchange light with the wavelength routing element. The wavelength routing element is of the type adapted for selectively routing wavelength components of a first optical signal onto multiple second optical signals according to a configurable state.

Abstract: In accordance with one embodiment, a processing method and apparatus is provided for partitioning exposed areas created by motion compensation. The partitioning creates sub-areas in shapes and sizes that may be effectively dealt with and efficiently compressed. The partitioning may divide an arbitrarily shaped area by “pinching,” “slicing,” and/or “cleaving” the area into manageable sub-areas. In accordance with another embodiment, a method and apparatus is provided for processing points in a bounded area to locate a medial axis. In accordance with another embodiment, an electronically-implemented method and apparatus is provided for processing a bounded two-dimensional area in an array of points to determine, for each point inside the area, a nearest boundary point outside the area as measured by a Euclidean distance.

Abstract: A method is provided for preventing dopant leaching from a doped structural film during fabrication of a microelectromechanical system. A microstructure that includes the doped structural film, sacrificial material, and metallic material is produced with a combination of deposition, patterning, and etching techniques. The sacrificial material is dissolved with a release solution that has a substance destructive to the sacrificial material. This substance also acts as an electrolyte, forming a galvanic cell with the doped structural film and metallic material acting as electrodes. The effects of the galvanic cell are suppressed by including a nonionic detergent mixed in the release solution.

Abstract: An apparatus and method for housing an optical element are provided. A ring is configured with a symmetry that corresponds to that of the optical element and for bonding with the optical element on an optical surface at a periphery of the optical element. An axial retaining spring may be provided for securing the optical element within an optical-system assembly. The axial retaining spring includes axial constraint fingers to engage a subsequent optical component and structures adapted to apply a point load at selected locations on the optical element.

Abstract: A microstructure for steering light is provided that mitigates stiction. A substrate is provided on which a structural linkage is connected to support a structural film. The structural film includes a reflective coating. A hold electrode is connected with the substrate at a position laterally beyond an orthogonal projection of the structural film on the substrate. It is configured to hold the structural film electrostatically in a tilted position with respect to the substrate upon application of a potential difference between the structural film and the hold electrode. Because of its positioning with respect to the structural film, it is ensured that the structural film is not in contact with the substrate when the structural film is being held by the hold electrode.

Abstract: Port priorities are defined on a 32-bit word, 16-bit half-word, and 8-bit byte basis to control the write enable signals to a compute register file (CRF). With a manifold array (ManArray) reconfigurable register file, it is possible to have double-word 64-bit and single word 32-bit data-type instructions mixed with other double-word, single-word, half-word, or byte data-type instructions within the same very long instruction word (VLIW). By resolving a write priority conflict on the byte, half-word, or word that is in conflict during the VLIW execution, it is possible to have partial operations complete that provide a useful function. For. example, a load half-word to the half-word H0 portion of a 32-bit register R0 can have priority to complete its operation while a 64-bit shift of the register pair R0 and R1 will complete its operation on the non-conflicting half-word portions of the 64-bit register R0 and R1.

Abstract: A hierarchical instruction set architecture (ISA) provides pluggable instruction set capability and support of array processors. The term pluggable is from the programmer's viewpoint and relates to groups of instructions that can easily be added to a processor architecture for code density and performance enhancements. One specific aspect addressed herein is the unique compacted instruction set which allows the programmer the ability to dynamically create a set of compacted instructions on a task by task basis for the primary purpose of improving control and parallel code density. These compacted instructions are parallelizable in that they are not specifically restricted to control code application but can be executed in the processing elements (PEs) in an array processor. The ManArray family of processors is designed for this dynamic compacted instruction set capability and also supports a scalable array of from one to N PEs.

Abstract: Techniques are described for semiconductor chips with reduced capacitive power dissipation as a result of improved conductor line spacing. The approaches are particularly applicable to 0.25 micron chip design processes and below. According to one aspect, where there are n available metallization layers available to the designer, a smaller number of layers, such as n−1, are utilized initially in developing a routing design. Then, at least one further metallization layer is used to systematically route conductors, such as bus conductors, to increase the number of metal pitches between conductors, by promoting conductors from one layer to another.

Abstract: Techniques for adding more complex instructions and their attendant multi-cycle execution units with a single instruction multiple data, stream (SIMD) very long instruction word (VLIW) processing framework are described. In one aspect, an initiation mechanism also acts as a resynchronization mechanism to read the results of multi-cycle execution. This multi-purpose mechanism operates with a short instruction word (SIW) issue of the multi-cycle instruction, in a sequence processor (SP) alone, with a VLIW, and across all processing elements (PEs) individually or as an array of PEs. A number of advantageous floating point instructions are also described.