Abstract: Efficient techniques for computation of texture coordinates using scaled conversion operations for a 3D graphics pipeline utilizing a scaled floating point to integer instruction and a scaled integer to floating point instruction to significantly reduce memory requirements. A parallel array VLIW digital signal processor is employed along with specialized scaled conversion instructions and communication operations between the processing elements, which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs are used allowing the graphics pipeline hardware to be efficiently used.

Abstract: A number of methods and systems for overcoming stiction are provided. The systems include electro-mechanical systems capable of exerting a variety of forces upon areas prone to stiction. The systems can be MEMS arrays or other types of devices where stiction related forces occur. The methods include a variety of ways of causing movement in areas prone to stiction forces. Such movement can be vibrational in nature and is sufficient to overcome stiction, allowing a trapped element to be moveed to a desired location.

Abstract: A configuration is provided by which it may be determined whether a MEMS device is in a select state. The select state is defined by a position of a moveable element, which is moved with electrostatic forces upon activation of an electrode. The select state is detected with a sensing configuration that has first and second regions. The regions are generally separated such that they are electrically uncoupled unless the moveable element is in the position that defines the select state. A detector may be provided to indicate whether the first and second regions are coupled electrically.

Abstract: A wavelength router is provided for receiving, at an input port, light having a plurality of spectral bands and directing some of those spectral bands to various output ports. The wavelength router includes an optical arrangement configured to provide optical paths for routing the spectral bands between the input and the output ports. A routing mechanism within the wavelength router has at least one dynamically configurable routing element to direct a given spectral band to different output ports, depending on the state of the dynamically configurable element. The wavelength router also includes a polarization-rotation element disposed with respect to the optical arrangement and the routing mechanism to be encountered by each optical path at least twice.

Abstract: Details of a highly cost effective and efficient implementation of a manifold array (ManArray) architecture and instruction syntax for use therewith are described herein. Various aspects of this approach include the regularity of the syntax, the relative ease with which the instruction set can be represented in database form, the ready ability with which tools can be created, the ready generation of self-checking codes and parameterized testcases. Parameterizations can be fairly easily mapped and system maintenance is significantly simplified.

Abstract: A reflective lamellar diffraction grating is provided that is suitable for a variety of applications, including applications related to C-band telecommunication functions. The average efficiency of the diffraction grating in S- and P-polarization states exceeds 90% while simultaneously providing a PDL less than 0.2 dB over the entire wavelength range used for C-band telecommunication functions. The diffraction grating is thus suitable for incorporation into various telecommunication systems, including a wavelength router configured for routing signals having a plurality of spectral bands.

Abstract: General purpose flags (ACFs) are defined and encoded utilizing a hierarchical one-, two- or three-bit encoding. Each added bit provides a superset of the previous functionality. With condition combination, a sequential series of conditional branches based on complex conditions may be avoided and complex conditions can then be used for conditional execution. ACF generation and use can be specified by the programmer. By varying the number of flags affected, conditional operation parallelism can be widely varied, for example, from mono-processing to octal-processing in VLIW execution, and across an array of processing elements (PE)s. Multiple PEs can generate condition information at the same time with the programmer being able to specify a conditional execution in one processor based upon a condition generated in a different processor using the communications interface between the processing elements to transfer the conditions.

Abstract: A number of methods and systems for overcoming stiction are provided. The systems include electromechanical systems capable of exerting a variety of forces upon areas prone to stiction. The systems can be MEMS arrays or other types of devices where stiction related forces occur. The methods include a variety of ways of causing movement in areas prone to stiction forces. Such movement can be vibrational in nature and is sufficient to overcome stiction, allowing a trapped element to be moveed to a desired location.

Abstract: Port priorities are defined on a 32-bit word, 16-bit half-word, and 8-bit byte basis to control the write enable signals to a compute register file (CRF). With a manifold array (ManArray) reconfigurable register file, it is possible to have double-word 64-bit and single word 32-bit data-type instructions mixed with other double-word, single-word, half-word, or byte data-type instructions within the same very long instruction word (VLIW). By resolving a write priority conflict on the byte, half-word, or word that is in conflict during the VLIW execution, it is possible to have partial operations complete that provide a useful function. For example, a load half-word to the half-word H0 portion of a 32-bit register R0 can have priority to complete its operation while a 64-bit shift of the register pair R0 and R1 will complete its operation on the non-conflicting half-word portions of the 64-bit register R0 and R1.

Abstract: A processor with a generalized eventpoint architecture, which is scalable for use in a very long instruction word (VLIW) array processor, such as the manifold array (ManArray) processor is described. In one aspect, generalized processor event (p-event) detection facilities are provided by use of compares to check if an instruction address, a data memory address, an instruction, a data value, arithmetic-condition flags, or other processor change of state eventpoint has occurred. In another aspect, generalized processor action (p-action) facilities are provided to cause a change in the program flow by loading the program counter with a new instruction address, generate an interrupt, signal a semaphore, log or count the p-event, time stamp the event, initiate a background operation, or to cause other p-actions to occur.

Abstract: The present invention provides improved MEMS devices and methods for use with fiber-optic communications systems. In one embodiment, an apparatus for steering light has a beam layer (160) with a reflective surface. The device uses a multi-layer electrode stack underlying the beam layer to rotate the beam layer into a desired position. Additionally, an underlying rotation and support structure provides a stable platform for the beam layer when the device is activated. In one embodiment, the underlying structure provides a multi-point landing system to maintain a generally flat beam layer upper surface when the device is activated.

Abstract: A processor or processor core has register file circuitry having a plurality of physical registers and a plurality of tag storing portions corresponding respectively to the physical registers. Each tag storing portion stores a tag representing a logical register ID allocated to the corresponding physical register. A register selection unit receives a logical register ID and selects one of the logical registers whose tag matches the received logical register ID. A tag changing unit changes the stored tags so as to change a mapping between at least one logical register ID and one of the physical registers. Such register circuitry permits a mapping between logical register IDs and physical registers to be changed quickly efficiently and can permit a desired physical register to be selected quickly.

Abstract: A variety of advantageous mechanisms for improved data transfer control within a data processing system are described. A DMA controller is described which is implemented as a multiprocessing transfer engine supporting multiple transfer controllers which may work independently or in cooperation to carry out data transfers, with each transfer controller acting as an autonomous processor, fetching and dispatching DMA instructions to multiple execution units. In particular, mechanisms for initiating and controlling the sequence of data transfers are provided, as are processes for autonomously fetching DMA instructions which are decoded sequentially but executed in parallel.

Abstract: Techniques for adding more complex instructions and their attendant multi-cycle execution units with a single instruction multiple data stream (SIMD) very long instruction word (VLIW) processing framework are described. In one aspect, an initiation mechanism also acts as a resynchronization mechanism to read the results of multi-cycle execution. This multi-purpose mechanism operates with a short instruction word (SIW) issue of the multi-cycle instruction, in a sequence processor (SP) alone, with a VLIW, and across all processing elements (PEs) individually or as an array of PEs. A number of advantageous floating point instructions are also described.

Abstract: A method of monitoring input light having a plurality of spectral bands (wavelength channels) includes the following, carried out for at least two different spectral bands at different times, using a common photodetector and wavelength-monitoring circuit that is coupled to the photodetector: separating one of the spectral bands from the plurality of spectral bands, directing light in only that spectral band to the photodetector, and generating, with the wavelength-monitoring circuit, a signal representing a quality characteristic of a modulated or unmodulated pattern of light in that spectral band. Each of the plurality of spectral bands can be individually and sequentially monitored in round-robin fashion, each of a subset of the spectral bands can be individually and sequentially monitored in round-robin fashion (to provide selective wavelength monitoring), or the monitoring can be ad hoc in response to external requirements.

Abstract: General purpose flags (ACFs) are defined and encoded utilizing a hierarchical one-, two- or three-bit encoding. Each added bit provides a superset of the previous functionality. With condition combination, a sequential series of conditional branches based on complex conditions may be avoided and complex conditions can then be used for conditional execution. ACF generation and use can be specified by the programmer. By varying the number of flags affected, conditional operation parallelism can be widely varied, for example, from mono-processing to octal-processing in VLIW execution, and across an array of processing elements (PE)s. Multiple PEs can generate condition information at the same time with the programmer being able to specify a conditional execution in one processor based upon a condition generated in a different processor using the communications interface between the processing elements to transfer the conditions.

Abstract: The ManArray processor is a scalable indirect VLIW array processor that defines two preferred architectures for indirect VLIW memories. One approach treats the VIM as one composite block of memory using one common address interface to access any VLIW stored in the VIM. The second approach treats the VIM as made up of multiple smaller VIMs each individually associated with the functional units and each individually addressable for loading and reading during XV execution. The VIM memories, contained in each processing element (PE), are accessible by the same type of LV and XV Short Instruction Words (SIWs) as in a single processor instantiation of the indirect VLIW architecture. In the ManArray architecture, the control processor, also called a sequence processor (SP), fetches the instructions from the SIW memory and dispatches them to itself and the PEs. By using the LV instruction, VLIWs can be loaded into VIMs in the SP and the PEs.

Abstract: A microstructure for steering light that mitigates stiction problems is provided. A first tiltable assembly that includes a reflective coating is connected with a substrate. A second tiltable assembly is also connected with the substrate. First and second electrodes are connected with the substrate and are configured to tilt the two tiltable assemblies such that they are interdigitated. In various embodiments, the tiltable assemblies are configured as cantilever arrangements and/or torsion-beam arrangements.

Abstract: General purpose flags (ACFs) are defined and encoded utilizing a hierarchical one-, two- or three-bit encoding. Each added bit provides a superset of the previous functionality. With condition combination, a sequential series of conditional branches based on complex conditions may be avoided and complex conditions can then be used for conditional execution. ACF generation and use can be specified by the programmer. By varying the number of flags affected, conditional operation parallelism can be widely varied, for example, from mono-processing to octal-processing in VLIW execution, and across an array of processing elements (PE)s. Multiple PEs can generate condition information at the same time with the programmer being able to specify a conditional execution in one processor based upon a condition generated in a different processor using the communications interface between the processing elements to transfer the conditions.

Abstract: A new motion estimation system and process for video compression is presented. The approach is computationally less expensive than typical spatial domain block matching algorithms. The search for matching blocks is performed in the frequency domain making extensive use of data already computed by the video encoding process. Moreover, additional good block matches can be recognized with this approach. A multi-tiered approach may be employed to combine the frequency domain analysis with existing spatial domain techniques.