Patents Assigned to Qorvo US, Inc.
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Patent number: 12388429Abstract: Group delay determination in a communication circuit is disclosed. The communication circuit includes a power amplifier circuit that amplifies a radio frequency (RF) signal based on a modulated voltage and a power management integrated circuit (PMIC) that generates the modulated voltage. Herein, the PMIC includes a group delay determination circuit to determine a relative group delay between the modulated voltage and a modulated current, which is internal to the power amplifier circuit and unknown to the PMIC, solely based on signals known to the PMIC. The determined relative group delay can help to time align the modulated voltage with the modulated current at the power amplifier circuit to improve error vector magnitude (EVM) and/or adjacent channel leakage ratio (ACLR). Further, by determining the relative group delay based on known signals to the PMIC, it is possible to achieve good time alignment between the modulated voltage and the modulated current.Type: GrantFiled: October 5, 2022Date of Patent: August 12, 2025Assignee: Qorvo US, Inc.Inventors: Marcus Granger-Jones, Nadim Khlat
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Patent number: 12381524Abstract: A multi-voltage power generation circuit is disclosed. More specifically, the multi-voltage generation circuit includes multiple voltage modulation circuits that are configured to generate and maintain multiple modulated voltages. In a non-limiting example, the multiple modulated voltages can be used for amplifying multiple radio frequency (RF) signals concurrently. Contrary to using multiple direct-current (DC) to DC (DC-DC) converters for generating the multiple modulated voltages, the voltage modulation circuits are configured to share a single current modulation circuit based on time-division. By sharing a single current modulation circuit among the multiple voltage modulation circuits, it is possible to concurrently support multiple load circuits (e.g., power amplifier circuits) with significantly reduced footprint.Type: GrantFiled: September 16, 2022Date of Patent: August 5, 2025Assignee: Qorvo US, Inc.Inventor: Nadim Khlat
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Patent number: 12381514Abstract: A power management circuit supporting phase correction in an analog signal is disclosed. The power management circuit includes a power amplifier circuit configured to amplify an analog signal having a time-variant power envelope based on a modulated voltage. The power management circuit also includes an envelope tracking (ET) integrated circuit (ETIC) configured to generate the modulated voltage and a modulated phase correction voltage to thereby cause a phase change in the analog signal. In embodiments disclosed herein, a correlation between the time-variant power envelope, the modulated voltage, and the modulated phase correction voltage is explored to thereby allow the ETIC to generate the modulated voltage and the modulated phase correction voltage based on the time-variant power envelope. As a result, it is possible to enable good time and phase alignment between the modulated voltage and the time-variant power envelope to thereby improve efficiency and linearity of the power amplifier circuit.Type: GrantFiled: November 29, 2021Date of Patent: August 5, 2025Assignee: Qorvo US, Inc.Inventors: Andrew F. Folkmann, Nadim Khlat, Mark Connor
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Patent number: 12381525Abstract: The present disclosure relates to an amplifier system having an output amplifier stage with a signal input and output, and a varactor with a capacitive output that is coupled to the signal input for adjusting input capacitance. The amplifier system also includes push varactor bias circuitry with a bias level output that is coupled to a tuning input, and a bias control input. The push varactor bias circuitry is configured to adjust bias voltage at the tuning input and thereby adjust the capacitance at the signal input by way of the varactor and reduce signal distortion at the signal output in response to a distortion compensation signal received at the bias control input.Type: GrantFiled: June 14, 2023Date of Patent: August 5, 2025Assignee: Qorvo US, Inc.Inventors: George Maxim, Nadim Khlat, Baker Scott, Kevin Wesley Kobayashi
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Patent number: 12381521Abstract: A distributed power management circuit is disclosed. Herein, a phase correction in a radio frequency (RF) signal is performed by a power management integrated circuit (PMIC), a distributed PMC, and a power amplifier circuit. The power amplifier circuit includes a phase shifter circuit configured to phase-shift the RF signal based on a phase correction signal and a power amplifier configured to amplify the phase-shifted RF signal based on a modulated voltage. The distributed PMIC is configured to generate the phase correction signal and the modulated voltage based on a modulated target voltage. The PMIC is configured to generate the modulated target voltage based on a time-variant power envelope of the RF signal. As a result, the modulated voltage and the time-variant power envelope can be better aligned in time and/or phase at the power amplifier circuit to thereby improve efficiency and linearity of the power amplifier.Type: GrantFiled: December 29, 2021Date of Patent: August 5, 2025Assignee: Qorvo US, Inc.Inventor: Nadim Khlat
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Patent number: 12375064Abstract: An acoustic transformer in a transmitter chain is disclosed. In one aspect, a differential power amplifier may produce a differential signal that is provided to an acoustic transformer coupled to an acoustic filter. The acoustic transformer provides a single-ended output signal for use by the acoustic filter. To facilitate operation in multiple bands, multiple acoustic transformer-acoustic filter pairs may be provided with a switching network used to route the amplified signal to the appropriate transformer-filter pair.Type: GrantFiled: September 1, 2023Date of Patent: July 29, 2025Assignee: Qorvo US, Inc.Inventors: Baker Scott, Nadim Khlat
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Patent number: 12375045Abstract: A reconfigurable amplifier configured to decrease radio frequency (RF) signal distortion and increase dynamic range is disclosed. The reconfigurable amplifier includes an amplifier having an RF signal input, an RF signal output, and a bias signal input. A distortion detection network has a detector input coupled to the RF signal output and a detector output, wherein the distortion detector network is configured to generate a detection signal that is proportional to distortion at the RF signal output. A bias controller has a detection signal input coupled to the detector output and a bias output coupled to the bias signal input. The bias controller is configured to generate a bias signal that dynamically shifts level at the bias output to reduce the distortion at the RF signal output in response to the detection signal.Type: GrantFiled: July 29, 2020Date of Patent: July 29, 2025Assignee: Qorvo US, Inc.Inventor: Kevin Wesley Kobayashi
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Patent number: 12375063Abstract: Disclosed is a filter bank die having a first acoustic wave (AW) filter having a first antenna terminal and a first filter terminal, and a second AW filter having a second filter terminal, and a second antenna terminal coupled to the first antenna terminal to effectively diplex signals that pass through the first AW filter and the second AW filter.Type: GrantFiled: June 9, 2021Date of Patent: July 29, 2025Assignee: Qorvo US, Inc.Inventors: Gangadhar Burra, Bror Peterson, Richard Perkins, Chris Levesque
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Patent number: 12375040Abstract: A virtual radio frequency (VRF) equalizer for an envelope tracking integrated circuit (ETIC) is disclosed. In one aspect, an ETIC provides envelope tracking (ET) for a barely Doherty (BD) power amplifier stage. The VRF equalizer includes circuitry that provides ripple cancelation that is caused by load modulation of the BD power amplifier stage. Additional circuitry is included to compensate for an amplifier within the ETIC. By canceling the ripple within the ETIC, the overall performance and efficiency of the BD power amplifier stage is improved, resulting in better performance of a transmitter in a wireless communication device.Type: GrantFiled: March 11, 2022Date of Patent: July 29, 2025Assignee: Qorvo US, Inc.Inventor: Nadim Khlat
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Patent number: 12368418Abstract: A power amplifier using multi-path common-mode feedback loops for radio frequency linearization is disclosed. In one aspect, a complementary metal oxide semiconductor (CMOS) power amplifier containing cascoded n-type field effect transistors (NFETs) and cascoded p-type FETs (PFETs) may have a common-mode feedback network and provides bias voltages that are dynamically varying with the signal power to keep the output common-mode fixed around a half-supply level, while the small-signal and large-signal transconductances of the FET's are kept balanced. A further feedback network may be associated with the supply voltage to assist in providing a symmetrical supply signal. The symmetrical supply signal allows for supply variations without introducing distortion for the power amplifier stage.Type: GrantFiled: January 31, 2022Date of Patent: July 22, 2025Assignee: Qorvo US, Inc.Inventors: Baker Scott, George Maxim, Stephen James Franck
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Patent number: 12365979Abstract: A structure includes a substrate including a wafer or a portion thereof; and a piezoelectric bulk material layer comprising a first portion deposited onto the substrate and a second portion deposited onto the first portion, the second portion comprising an outer surface having a surface roughness (Ra) of 4.5 nm or less. Methods for depositing a piezoelectric bulk material layer include depositing a first portion of bulk layer material at a first incidence angle to achieve a predetermined c-axis tilt, and depositing a second portion of the bulk material layer onto the first portion at a second incidence angle that is smaller than the first incidence angle. The second portion has a second c-axis tilt that substantially aligns with the first c-axis tilt.Type: GrantFiled: December 20, 2023Date of Patent: July 22, 2025Assignee: Qorvo US, Inc.Inventors: Derya Deniz, Matthew Wasilik, Robert Kraft, John Belsick
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Patent number: 12362730Abstract: A single pole double throw (SPDT) switch with embedded attenuators includes a transmitter attenuator circuit directly connected to a common input of the SPDT switch, and a receiver attenuator circuit directly connected to the common input of the SPDT switch. Switches in the transmitter attenuator circuit and in the receiver attenuator circuit are selectively or individually set to an open state or to a closed state to directly connect the transmitter attenuator circuit or the receiver attenuator circuit to the common input. The selective setting of the states of the switches also determines a given amount of attenuation for the transmitter attenuator circuit or the receiver attenuator circuit.Type: GrantFiled: November 18, 2022Date of Patent: July 15, 2025Assignee: Qorvo US, Inc.Inventors: Jinsung Choi, Marcus Granger-Jones, Jeffery Peter Ortiz
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Patent number: 12362728Abstract: An acoustic transformer in a transmitter chain is disclosed. In one aspect, a differential power amplifier may produce a differential signal that is provided to a first transformer. A differential output of this first transformer is provided to an acoustic transformer that provides a single ended output signal for use by an acoustic filter. By making the second transformer an acoustic transformer, the second transformer may be integrated into the same circuitry that forms the acoustic filter, thereby simplifying the die. Further, the acoustic transformer may be tuned if ferroelectric resonators are used, which provides strong out-of-band signal cancelation.Type: GrantFiled: July 11, 2023Date of Patent: July 15, 2025Assignee: Qorvo US, Inc.Inventor: Nadim Khlat
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Patent number: 12354821Abstract: Embodiments of the disclosure are directed to microelectromechanical system (MEMS) switches with a beam contact portion continuously extending between input and output terminal electrodes. In exemplary aspects disclosed herein, the movable beam includes a body and a contact with more conductivity and stiffness than the body. The contact continuously extends between and electrically couples the contact of the movable beam with the input and output terminal electrodes. Differing materials between the body and the contact allow for inclusion of the mechanical properties of the body (e.g., to reduce mechanical fatigue, creep, etc.) while utilizing the electrical properties of the contact (e.g., to reduce on-state electrical resistance). Accordingly, the MEMS switch provides low resistance loss during an on-state while maintaining high levels of isolation during an off-state.Type: GrantFiled: May 22, 2024Date of Patent: July 8, 2025Assignee: Qorvo US, Inc.Inventor: Robertus Petrus Van Kampen
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Patent number: 12353643Abstract: Methods and systems related to the field of pointing devices are disclosed herein. One disclosed device has a pointing direction, a set of antennas including a first antenna and a second antenna, and at least one of an inertial measurement unit, a gravity sensor, and a magnetometer. The device also includes one or more computer readable media storing instructions which, when executed on the device, cause the device to: determine a difference between a signal as received by the first antenna and the signal as received by the second antenna; determine, using the difference, an angle between the pointing direction and a signal source direction of the signal; measure a physical quantity using the at least one of the inertial measurement unit, the gravity sensor, and the magnetometer; and determine a pointing target of the device using the angle and the physical quantity.Type: GrantFiled: January 28, 2021Date of Patent: July 8, 2025Assignee: Qorvo US, Inc.Inventors: Julien Colafrancesco, Nicolas Schodet
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Patent number: 12342518Abstract: The disclosure relates to a shielded electronic module which includes a module shielding structure and an electronic module with an interposer, a shielded electronic submodule over the interposer, and a module mold compound over the interposer and encapsulating sides of the shielded electronic submodule. Herein, the shielded electronic submodule includes an electronic submodule and a submodule side shielding structure, which covers sides of the electronic submodule to provide the sides of the shielded electronic submodule. A top surface of the electronic module is a combination of a top surface of the module mold compound and a top surface of the shielded electronic submodule, which is not covered by the module mold compound. The module shielding structure directly and continuously covers the top surface and sides of the electronic module, such that the submodule side shielding structure is electrically connected to the module shielding structure to individually shield the electronic submodule.Type: GrantFiled: January 23, 2023Date of Patent: June 24, 2025Assignee: Qorvo US, Inc.Inventors: Thomas Scott Morris, Howard Terry Glascock, Charles E. Carpenter, Mudar Al-Joumayly, Peter Cotterill
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Patent number: 12340787Abstract: Embodiments described herein may provide a surface acoustic wave (SAW) device, methods of fabricating the SAW device, and a system incorporating the SAW device. The SAW device may include a piezoelectric substrate and individual resonators may be formed by a plurality of electrodes on the surface of the piezoelectric substrate. A dielectric layer having a positive thermal coefficient of frequency (TCF) may be formed on each of the plurality of electrodes. In various embodiments, temperature compensation may be achieved by providing more or less of the dielectric layer on at least one resonator than on the other resonators based on a configuration of the resonators. In various embodiments, temperature compensation may be achieved by providing at least one resonator with a different duty factor than the other resonators based on a configuration of the resonators.Type: GrantFiled: September 26, 2023Date of Patent: June 24, 2025Assignee: Qorvo US, Inc.Inventor: Marc Solal
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Semiconductor device and method of manufacturing a semiconductor device using multiple CMP processes
Patent number: 12341023Abstract: A method of manufacturing a semiconductor device includes performing one or more grinding processes on a backside surface of a device wafer to thin the device wafer from a first thickness to a second thickness. A first chemical mechanical polish (CMP) process is performed on the backside surface of the device wafer to thin the device wafer from the second thickness to a third thickness. A second CMP process is performed on the backside surface of the device wafer to selectively remove device wafer material that is disposed over an active device area of the semiconductor device, where a removal rate of the device wafer material is a function of depth.Type: GrantFiled: June 10, 2022Date of Patent: June 24, 2025Assignee: Qorvo US, Inc.Inventors: Krishna Chetry, Ganesan Radhakrishnan -
Patent number: 12335073Abstract: Intra-symbol voltage modulation in a wireless communication circuit is disclosed. In a wireless communication circuit, a power amplifier circuit is configured to amplify a radio frequency (RF) signal based on a modulated voltage that tracks a time-variant input power of the RF signal. Herein, intra-symbol voltage modulation means that the modulated voltage can be adapted within a voltage modulation interval(s), such as an orthogonal frequency division multiplexing (OFDM) symbol duration. In embodiments disclosed herein, the voltage modulation interval(s) is divided into multiple voltage modulation subintervals and a respective voltage target is determined for each of the voltage modulation subintervals. Accordingly, the modulated voltage can be adapted in each of the voltage modulation subintervals according to the respective voltage target.Type: GrantFiled: October 31, 2022Date of Patent: June 17, 2025Assignee: Qorvo US, Inc.Inventor: Nadim Khlat
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Patent number: 12334413Abstract: The present disclosure relates to a system in package having a chiplet with a first substrate and a first die deposed over the first substrate, a second die, a second substrate that the chiplet and the second die are deposed over, and a heatsink spreader deposed over the chiplet and the second die. Herein, the first substrate includes layered-cake shaped heatsink stanchions that are coupled to the first die, and the second substrate includes layered-cake shaped heatsink stanchions that are coupled to the chiplet and the second die. As such, heat generated by the first die can be dissipated by the heatsink stanchions within the first and second substrates, and heat generated by the second die can be dissipated by the heatsink stanchions within the second substrate. Furthermore, the heat generated by the first die and the second die can be dissipated by the heatsink spreader above them.Type: GrantFiled: February 5, 2024Date of Patent: June 17, 2025Assignee: Qorvo US, Inc.Inventors: Kelly M. Lear, Jeffrey Miller, Mihir Roy, Christine Blair