Patents Assigned to Qorvo US, Inc.
  • Patent number: 10320379
    Abstract: Disclosed is a transistor-based switch having an N number of main field-effect transistors (FETs) stacked in series such that a first terminal of a first main FET of the N number of main FETs is coupled to a first end node and a second terminal of an Nth main FET of the N number of main FETs is coupled to a second end node, wherein N is a finite number greater than five. The transistor-based switch further includes a gate bias network having a plurality of gate resistors, wherein individual ones of the plurality of gate resistors are coupled to gate terminals of the N number of main FETs. A common gate resistor is coupled between a gate control input and a gate control node of the plurality of gate resistors, and a capacitor is coupled between the gate control node and a switch path node of the main FETs.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: June 11, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Daniel Charles Kerr, Jinsung Choi, Baker Scott, George Maxim, Hideya Oshima
  • Patent number: 10312960
    Abstract: A switchable RF transmit/receive (TX/RX) multiplexer, which includes a group of RF TX bandpass filters, a group of RF TX switching elements, and a group of RF RX bandpass filters; is disclosed. The group of RF TX bandpass filters includes a first RF TX bandpass filter and a second RF TX bandpass filter, such that each of the first RF TX bandpass filter and the second RF TX bandpass filter is coupled to a first filter connection node. The group of RF TX switching elements includes a first RF TX switching element coupled between the first filter connection node and a first common connection node, which is coupled to a first RF antenna. Each of the group of RF RX bandpass filters is coupled to the first common connection node.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: June 4, 2019
    Assignee: Qorvo US, Inc.
    Inventor: Nadim Khlat
  • Patent number: 10305443
    Abstract: A micro-electrical-mechanical system (MEMS) guided wave device includes a plurality of electrodes arranged below a piezoelectric layer (e.g., either embedded in a slow wave propagation layer or supported by a suspended portion of the piezoelectric layer) and configured for transduction of a lateral acoustic wave in the piezoelectric layer. The piezoelectric layer permits one or more additions or modifications to be made thereto, such as trimming (thinning) of selective areas, addition of loading materials, sandwiching of piezoelectric layer regions between electrodes to yield capacitive elements or non-linear elastic convolvers, addition of sensing materials, and addition of functional layers providing mixed domain signal processing utility.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: May 28, 2019
    Assignee: Qorvo US, Inc.
    Inventor: Kushal Bhattacharjee
  • Patent number: 10304753
    Abstract: The present disclosure relates to a thermally enhanced semiconductor package having field effect transistors (FETs) with a back-gate feature. The thermally enhanced semiconductor package includes a first buried oxide (BOX) layer, a first epitaxial layer over the first BOX layer, a second BOX layer over the first epitaxial layer, a second epitaxial layer over the second BOX layer and having a source, a drain, and a channel between the source and the drain, a gate dielectric aligned over the channel, and a front-gate structure over the gate dielectric. Herein, a back-gate structure is formed in the first epitaxial layer and has a back-gate region aligned below the channel. A FET is formed by the front-gate structure, the source, the drain, the channel, and the back-gate structure.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: May 28, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, George Maxim, Dirk Robert Walter Leipold, Baker Scott
  • Patent number: 10302595
    Abstract: A micro-electrical-mechanical system (MEMS) resonator device includes a top side electrode overlaid with a low water permeability hermeticity layer and an interface layer including a material (e.g., gold or a hydroxylated oxide surface) suitable for receiving a self-assembled monolayer (SAM) that may be functionalized with a functionalization (e.g., specific binding) material, with the foregoing layers being designed to have insubstantial impact on sensor performance. Atomic layer deposition may be used for deposition of the hermeticity and/or interface layers. The hermeticity layer protects the electrode material from attack in corrosive liquid environments, and the interface layer facilitates proper chemical binding of the SAM. Sensors and microfluidic devices incorporating MEMS resonator devices are also provided.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: May 28, 2019
    Assignee: QORVO US, INC.
    Inventors: John Belsick, Rick Morton, Matthew Ryder
  • Patent number: 10305442
    Abstract: A micro-electrical-mechanical system (MEMS) guided wave device includes a plurality of electrodes arranged below a piezoelectric layer (e.g., either embedded in a slow wave propagation layer or supported by a suspended portion of the piezoelectric layer) and configured for transduction of a lateral acoustic wave in the piezoelectric layer. The piezoelectric layer permits one or more additions or modifications to be made thereto, such as trimming (thinning) of selective areas, addition of loading materials, sandwiching of piezoelectric layer regions between electrodes to yield capacitive elements or non-linear elastic convolvers, addition of sensing materials, and addition of functional layers providing mixed domain signal processing utility.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: May 28, 2019
    Assignee: Qorvo US, Inc.
    Inventor: Kushal Bhattacharjee
  • Patent number: 10297529
    Abstract: The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the module substrate, a mold compound component, a thermally conductive film, and a thermally enhanced mold compound component. The mold compound component resides over the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die. The thermally conductive film resides over at least the upper surface of the thinned flip chip at the bottom of the cavity. The thermally enhanced mold compound component resides over at least a portion of the thermally conductive film to fill the cavity.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: May 21, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Robert Aigner
  • Patent number: 10297894
    Abstract: A spatial power-combining device and an antenna structure designed for high efficiency, high frequency, and ultra-wide bandwidth operation. The antenna structure may include a signal conductor and a ground conductor that are entirely separated by air. A spatial power-combining device may include a plurality of amplifier assemblies including multiple output antenna structures and an output coaxial waveguide section configured to concurrently combine signals received from each output antenna structure of the plurality of amplifier assemblies. The plurality of amplifier assemblies may also include multiple input antenna structures and an input coaxial waveguide configured to provide an input signal concurrently to each input antenna structure of the plurality of amplifier assemblies.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: May 21, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Ankush Mohan, Dan Denninghoff, John Kitt, Soack Yoon
  • Patent number: 10298186
    Abstract: A carrier aggregation front-end module with a receive sub-module for receiving signals from a plurality of transmit modules. The module comprises a first receive path configured to receive a first set of signals from one or more of a plurality of antennas, wherein the first set of signals comprises at least one desired receive signal and at least one undesired transmit blocker signal from the plurality of transmit modules. The second receive path is configured to receive a second set of signals from one or more of a plurality of antennas comprising at least one desired receive signal and at least one undesired transmit blocker signal from the plurality of transmit modules. The module also comprises at least one shared tunable notch filter configured to reject at least one of the undesired transmit blocker signals for each of the first receive path and the second receive path.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: May 21, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Dirk Robert Walter Leipold, George Maxim, Baker Scott
  • Patent number: 10298196
    Abstract: Embodiments of radio frequency (RF) filtering circuitry are disclosed. In one embodiment, the RF filtering circuitry includes a first port, a second port, a first RF filter path, and a second RF filter path. The first RF filter path is connected between the first port and the second port and includes at least a pair of weakly coupled resonators. The weakly coupled resonators are configured such that a first transfer response between the first port and the second port defines a first passband. The second RF filter path is coupled to the first RF filter path and is configured such that the first transfer response between the first port and the second port defines a stopband adjacent to the first passband without substantially increasing ripple variation of the first passband defined by the first transfer response.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: May 21, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Dirk Robert Walter Leipold, George Maxim, Marcus Granger-Jones, Baker Scott
  • Patent number: 10298288
    Abstract: This disclosure relates to antenna switching circuitry and other radio frequency (RF) front-end circuitry. In one embodiment, the antenna switching circuitry includes a multiple throw solid-state transistor switch (MTSTS), a multiple throw microelectromechanical switch (MTMEMS), and a control circuit. The MTSTS is configured to selectively couple a first pole port to any one of a first set of throw ports and to selectively couple a second pole port to any one of a second set of throw ports. The MTMEMS is configured to selectively couple a third pole port to any one of a third set of throw ports. The control circuit is configured to control the selective coupling of the MTSTS and the MTMEMS. In this manner, the control circuit may operate the antenna switching circuitry so that RF signals may be routed in accordance with Long Term Evolution (LTE) Multiple-Input and Multiple-Output (MIMO) and/or LTE diversity specifications.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: May 21, 2019
    Assignee: Qorvo US, Inc.
    Inventor: Nadim Khlat
  • Patent number: 10290713
    Abstract: A field-effect transistor having a transconductance (gm) that remains within 65% of a maximum gm value over at least 85% of a gate voltage range that transitions the field-effect transistor between an on-state that allows substantial current flow through the channel layer and an off-state that prevents substantial current flow through the channel layer is disclosed. The field-effect transistor includes a substrate and a channel layer having a proximal boundary relative to the substrate and a distal boundary relative to the substrate. The channel layer is disposed over the substrate and comprises a compound semiconductor material that includes at least one element having a concentration that is graded between the proximal boundary and the distal boundary.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: May 14, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Jinqiao Xie, Edward A. Beam, III
  • Patent number: 10291205
    Abstract: RF circuitry, which includes a first acoustic RF resonator (ARFR) and a first compensating ARFR, is disclosed. A first inductive element is coupled between the first compensating ARFR and a first end of the first ARFR. A second inductive element is coupled between the first compensating ARFR and a second end of the first ARFR. The first compensating ARFR, the first inductive element, and the second inductive element at least partially compensate for a parallel capacitance of the first ARFR.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: May 14, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Nadim Khlat, Jean-Frederic Chiron, Marcus Granger-Jones, Andrew F. Folkmann, Robert Aigner
  • Patent number: 10290632
    Abstract: Alternating Current (AC)-coupled switch and metal capacitor structures for nanometer or low metal layer count processes are provided. According to one aspect of the present disclosure, a switch and capacitor structure comprises a substrate comprising a device region with a Field Effect Transistor (FET) formed therein, the FET having a source terminal comprising a structure in a first metal layer and a drain terminal comprising a structure in the first metal layer, and a capacitor comprising a first plate and a second plate, the first plate comprising a structure in a second metal layer, the second metal layer being above the first metal layer, the structure of the first plate being electrically connected to the structure of the drain terminal, and the second plate comprising a structure in the second metal layer, the structure of the first plate spaced from the structure of the second plate.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: May 14, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Baker Scott, George Maxim, Dirk Robert Walter Leipold, Marcus Granger-Jones
  • Patent number: 10291191
    Abstract: The present disclosure relates to a radio frequency (RF) communications system including an RF power amplifier (PA), a bias circuit, and a protection circuit. The RF PA has an amplifier control terminal and a power supply terminal, the bias circuit is coupled to the amplifier control terminal, and the protection circuit is coupled between the bias circuit and the power supply terminal. Herein, the protection circuit is configured to reduce a current through the power supply terminal using the bias circuit via the amplifier control terminal when the RF PA is in an operation mode and a magnitude of a voltage at the power supply terminal exceeds a protection threshold. Further, the protection circuit is configured to be open and does not allow a current to pass through when the RF PA is in a standby mode.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: May 14, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Douglas Andrew Teeter, Nick Marcoux, Ming Ji
  • Patent number: 10284178
    Abstract: Embodiments of radio frequency (RF) filtering circuitry are disclosed. In one embodiment, the RF filtering circuitry includes a common port, a second port, a third port, a first RF filter path, and a second RF filter path. The first RF filter path is connected between the common port and the second port and comprises a first pair of resonators and a first acoustic wave resonator. One of the first pair of resonators also includes a second acoustic wave resonator. The second RF filter path is connected between the common port and the third port. The second RF filter path includes a second pair of resonators. The first and second acoustic wave resonators of the first RF filter path increase roll-off greatly with respect to just an LC filter, and thereby allow for an increase out-of-band rejection at high frequency ranges.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: May 7, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Dirk Robert Walter Leipold, George Maxim, Marcus Granger-Jones, Baker Scott
  • Patent number: 10284176
    Abstract: Embodiments described herein may provide a surface acoustic wave (SAW) device, methods of fabricating the SAW device, and a system incorporating the SAW device. The SAW device may include a piezoelectric substrate and individual resonators may be formed by a plurality of electrodes on the surface of the piezoelectric substrate. A dielectric layer having a positive thermal coefficient of frequency (TCF) may be formed on each of the plurality of electrodes. In various embodiments, temperature compensation may be achieved by providing more or less of the dielectric layer on at least one resonator than on the other resonators based on a configuration of the resonators. In various embodiments, temperature compensation may be achieved by providing at least one resonator with a different duty factor than the other resonators based on a configuration of the resonators.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: May 7, 2019
    Assignee: Qorvo US, Inc.
    Inventor: Marc Solal
  • Patent number: 10284412
    Abstract: An envelope tracking (ET) amplifier circuit is provided. The voltage mDPD circuit is provided in an ET amplifier circuit and configured to determine a voltage deviation relative to an ET modulated target voltage signal, execute an mDPD polynomial in one or more iterations to extract an mDPD coefficient(s), and adjust a time-variant target voltage envelope of the ET modulated target voltage signal based on the mDPD coefficient(s) extracted in each of the mDPD iterations to reduce the voltage deviation to a predefined threshold. By reducing the voltage deviation in the ET modulated voltage, it is possible improve linearity (e.g., gain linearity) of the ET amplifier circuit, which can lead to reduced power consumption and improved radio frequency (RF) performance.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: May 7, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Nadim Khlat, Jean-Frederic Chiron, Andrew F. Folkmann
  • Patent number: 10283480
    Abstract: The present disclosure relates to a substrate structure with selective surface finishes used in flip chip assembly, and a process for making the same. The disclosed substrate structure includes a substrate body, a metal structure with a first finish area and a second finish area, a first surface finish, and a second surface finish. The metal structure is formed on a top surface of the substrate body, the first surface finish is formed over the first finish area of the metal structure, and the second surface finish is formed over the second finish area of the metal structure. The first surface finish is different from the second surface finish.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: May 7, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Thomas Scott Morris, Robert Hartmann
  • Patent number: 10283494
    Abstract: The present disclosure relates to a microelectronics package with a self-aligned stacked-die assembly and a process for making the same. The disclosed microelectronics package includes a module substrate, a first die with a first coupling component, a second die with a second coupling component, and a first mold compound. The first die is attached to the module substrate. The first mold compound resides over the module substrate, surrounds the first die, and extends above an upper surface of the first die to define a first opening. Herein, the first mold compound provides vertical walls of the first opening, which are aligned with edges of the first die in X-direction and Y-direction. The second die is stacked with the first die and in the first opening, such that the second coupling component is mirrored to the first coupling component.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: May 7, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, George Maxim