Abstract: A memory mapping system for compactly mapping dissimilar memory systems and methods for manufacturing and using same. The mapping system maps a source memory system into a destination memory system by partitioning the source memory system and disposing memory contents within the partitioned source memory system into the destination memory system. In one embodiment, the mapping system factorizes a source data width of the source memory system in terms of a destination data width of the destination memory system to form at least one data sub-width. A source memory sub-region is defined for each data sub-width. The memory contents associated with each source memory sub-region are disposed within the destination memory system in a side-by-side manner across selected destination memory registers of the destination memory system. The mapping system thereby can compactly map the memory contents into the destination memory system without a loss of valuable memory space.

Abstract: A memory mapping system for providing compact mapping between dissimilar memory systems and methods for manufacturing and using same. The memory mapping system can compactly map contents from one or more first memory systems into a second memory system without a loss of memory space in the second memory system. Advantageously, the memory mapping system can be applied to hardware emulator memory systems to more efficiently map design memory systems into an emulation memory system during compilation.

Abstract: An identification system for identifying and validating selected components of a communication system and methods for manufacturing and using same. The communication system includes a host system that is configured to couple with one or more target systems. When the host system is coupled with a selected target system, the communication system can enter an identification mode wherein the selected target system can provide identification data to the host system. The identification data includes information regarding at least one target system characteristic associated with the selected target system such that the host system can attempt to identify the selected target system based at least in part upon the target system characteristics. Once the selected target system has been identified, the communication system likewise can at least partially reconfigure the host system, as necessary, such that the host system can be compatible with the selected target system.

Abstract: A target interface system for interfacing selected components of a communication system and methods for manufacturing and using same. The target interface system includes target interface logic that is distributed among a plurality of reconfigurable logic devices. Being coupled via a serial link, the reconfigurable logic devices each have an input connection for receiving incoming data packets and an output connection for providing outgoing data packets. The serial link couples the input and output connections of successive reconfigurable logic devices to form a dataring structure for distributing the data packets among the reconfigurable logic devices. Thereby, the dataring structure maintains data synchronization among the reconfigurable logic devices such that the distribution of the target interface logic among the reconfigurable logic devices is transparent to software.

Abstract: A signal conversion system for interfacing selected components of a communication system and methods for manufacturing and using same. The signal conversion system converts selected logic signals from one system component into a pair of differential logic signals and provides the pair of differential logic signals to a second system component, resolving any logical and/or temporal artifacts. While one or more of the selected logic signals change signal state, the signal conversion system maintains the pair of differential logic signals in a first valid combined signal state until the signal state of the selected logic signals corresponds to a second valid combined signal state for the pair of differential logic signals. The signal verification system then updates the pair of differential logic signals to have the second valid combined signal state. The system components thereby can communicate, exchanging differential communication signals while maintaining duty cycle and avoiding signaling glitches.

Abstract: Methods and apparatus, including computer program products, for emulating a memory circuit in a logic emulation system. The system includes at least one log memory associated with the emulated memory. Each log memory location is marked invalid at a predetermined time. The system receives one or more memory write requests after the predetermined time, each memory write request specifying new data to be written to a specified memory location. If a log memory location corresponding to the specified memory location is marked invalid, a pre-write content of the specified memory location is copied to the corresponding log memory location and the corresponding log memory location is marked as valid, prior to writing the new data at the specified memory location in the emulated memory. The emulated memory is restored to the predetermined time by copying a content of each log memory location marked valid to the emulated memory.

Abstract: The present system and methods are directed to the interconnection of clusters of emulation processors comprising emulation processors in a software-driven hardware design verification system. The processors each output one NBO output signal. The clusters are interconnected by partitioning a common NBO bus into a number of smaller NBO busses, each carrying unique NBO signals but together carrying every NBO. Each of the smaller NBO busses are passed into a series of multiplexers, each dedicated to a particular processor. The multiplexers select a signal for output back to the emulation clusters. The multiplexers that handle these smaller NBO busses are narrower than was previously required, thus reducing the amount of power, interconnect, and area required by the multiplexer array and dedicated interconnect.

Abstract: A method and apparatus for debugging circuit designs having random access memory therein. The circuit design is emulated on a hardware logic emulator. The RAM emulated by the emulator can be rewound to a previous state, and then replayed. The RAM emulated by the emulator can also be reconstructed to a state the RAM maintained at some point during a trace window.

Abstract: An improved emulation system having an improved trigger mechanism is disclosed. During the compilation of the circuit design, a portion of the emulation resources are reserved for dynamic netlists. The dynamic netlists allows a user to create arbitrary trigger circuits that can be based on any signal generated by the device under test during run time, including signals that were optimized out of the design during the compilation process. The dynamic netlists can be loaded and used in the emulator without having to recompile the entire design, which could take many hours. This enables a user to quickly and efficiently debug circuit designs.

Abstract: An optimized interface for simulation and visualization data transfer between an emulation system and simulator is disclosed. In one embodiment, a method of transferring data between a simulator to an emulator across an interface, comprises updating a simulator buffer of the simulator to contain a desired input state for an emulation cycle. A target write to the interface is performed to indicate that the emulation cycle can proceed. The emulation cycle is completed using an instruction sequencer within the interface independent of the simulator.

Abstract: A design verification system utilizing programmable logic devices having varying numbers of logic processors, macro processors, memory processors and general purpose processors programmed therein is disclosed. These various processors can execute Boolean functions, macro operations, memory operations, and other computer instructions. This avoids either the need to implement logic or the need to compile the design into many gate-level Boolean logic operations for logic processors. Improved efficiency in the form of lower cost, lower power and/or higher speeds are the result when verifying certain types of designs.

Abstract: A fully synthesizeable Simulation Control Module (SCM) controls and monitors the simulation of a design under test (DUT). A clock generator within the SCM and a Software clock facility residing on the host workstation are responsible for providing the clocks for the DUT. The SCM and the hardware clock facility are dynamically generated at build time to suit the needs of the DUT. They maximize performance by automatically generating clock waveforms for designs containing multiple asynchronous clocks, thereby decreasing the frequency of accelerator-workstation interaction. The software clock facility has the ability to directly drive the DUT and is responsible for managing the simulation time and clock parameters. The SCM is also responsible for monitoring an abort condition such as a trigger to execute an external software model. The SCM and the clock facilities allow the hardware accelerator to efficiently support multiple asynchronous clock domains, execution of external software models and co-simulation.

Abstract: A system is provided to increase the accessibility of registers and memories in a user's design undergoing functional verification in a hardware-assisted design verification system. A packet-based protocol is used to perform data transfer operations between a host workstation and a hardware accelerator for loading data to and unloading data from the registers and memories in a target design under verification (DUV) during logic simulation. The method and apparatus synthesizes interface logic into the DUV to provide for greater access to the registers and memories in the target DUV which is simulated with the assistance of the hardware accelerator.

Abstract: A mechanism is described for effecting the ejection of a high extraction force electromechanical connector from its mate by utilizing an ejector mechanism and without requiring custom design or manufacturing of the mating connector. One embodiment achieves this by way of rigid sliding frame which applies force to a portion of the mating connector which is otherwise intended to provide alignment guidance between the two connectors.

Abstract: Clusters of processors are interconnected as an emulation engine such that processors share input and data stacks, and the setup and storing of results are done in parallel, but the output of one evaluation unit is connected to the input of the next evaluation unit. A set of ‘cascade’ connections provides access to the intermediate values. By tapping intermediate values from one processor, and feeding them to the next, a significant emulation speedup is achieved.

Abstract: In an emulator processor cluster, the read ports of a shared input and data memory stack are time multiplexed to serve more than one processor. In an exemplary embodiment of the invention, a 256×8 memory array serves as the shared memory for four processors in a cluster. Two read ports are time multiplexed among the four processors in the cluster. On one read cycle, data from the two read ports is coupled to two processors. The next read cycle reads data from the same two ports to the remaining two processors. In the preferred embodiment, the memory operates at twice the system clock speed so that overall emulation process execution time is not effected.

Abstract: A system and method for bulk transfer to and from the SRAMs in which a starting memory address is latched and is then incremented every clock cycle to generate a new memory address. The addresses are decoded and memory requests are pipelined to the SRAM memory, one every clock cycle. When the memory controller detects transfer of the boundary of a predetermined number of clock cycles or words (e.g. 64 words or four clock cycles) the burst mode of data transfer is stopped and the memory controller waits for a “done” signal before resuming another cycle of the burst transfer mode. The memory controller on detecting a request on this address boundary first does a memory refresh followed by a requested operation; e.g. a continuation of the transfer operation.

Abstract: A programmable logic device architecture. This programmable logic architecture includes a first logic block (425) containing programmable logic elements for performing logic functions. The architecture may also include a diagnostic block interface (415), which interfaces with the first logic block (425), for performing JTAG functions, configuring the first logic block (425), initializing the first logic block (425), interfacing with off-chip diagnostic and test devices and equipment, and performing other similar functions. The first logic block (425) may be programmably coupled to other components on the integrated circuit using a first programmable interconnect network (511). The first logic block (425) includes a plurality of second logic blocks (505) which may be programmably coupled using a second programmable interconnect network (521). The second programmable interconnect network (521) may be programmably coupled to the first programmable interconnect network (511).

Abstract: A software driven emulator has a maintenance bus operating protocol mode in which, after an initial address phase, data is streamed continuously by automatically incrementing the sending and receiving addresses.

Abstract: A system for physical emulation of electronic circuits or systems includes a data entry workstation where a user may input data representing the circuit or system configuration. This data is converted to a form suitable for programming an array of programmable gate elements provided with a richly interconnected architecture. Provision is made for externally connecting VLSI devices or other portions of a user's circuit or system a network of internal probing interconnections is made available by utilization of unused circuit paths in the programmable gate arrays.