Abstract: A mechanism is described for effecting the ejection of a high extraction force electromechanical connector from its mate by utilizing an ejector mechanism and without requiring custom design or manufacturing of the mating connector. One embodiment achieves this by way of rigid sliding frame which applies force to a portion of the mating connector which is otherwise intended to provide alignment guidance between the two connectors.

Abstract: Clusters of processors are interconnected as an emulation engine such that processors share input and data stacks, and the setup and storing of results are done in parallel, but the output of one evaluation unit is connected to the input of the next evaluation unit. A set of ‘cascade’ connections provides access to the intermediate values. By tapping intermediate values from one processor, and feeding them to the next, a significant emulation speedup is achieved.

Abstract: In an emulator processor cluster, the read ports of a shared input and data memory stack are time multiplexed to serve more than one processor. In an exemplary embodiment of the invention, a 256×8 memory array serves as the shared memory for four processors in a cluster. Two read ports are time multiplexed among the four processors in the cluster. On one read cycle, data from the two read ports is coupled to two processors. The next read cycle reads data from the same two ports to the remaining two processors. In the preferred embodiment, the memory operates at twice the system clock speed so that overall emulation process execution time is not effected.

Abstract: A system and method for bulk transfer to and from the SRAMs in which a starting memory address is latched and is then incremented every clock cycle to generate a new memory address. The addresses are decoded and memory requests are pipelined to the SRAM memory, one every clock cycle. When the memory controller detects transfer of the boundary of a predetermined number of clock cycles or words (e.g. 64 words or four clock cycles) the burst mode of data transfer is stopped and the memory controller waits for a “done” signal before resuming another cycle of the burst transfer mode. The memory controller on detecting a request on this address boundary first does a memory refresh followed by a requested operation; e.g. a continuation of the transfer operation.

Abstract: A programmable logic device architecture. This programmable logic architecture includes a first logic block (425) containing programmable logic elements for performing logic functions. The architecture may also include a diagnostic block interface (415), which interfaces with the first logic block (425), for performing JTAG functions, configuring the first logic block (425), initializing the first logic block (425), interfacing with off-chip diagnostic and test devices and equipment, and performing other similar functions. The first logic block (425) may be programmably coupled to other components on the integrated circuit using a first programmable interconnect network (511). The first logic block (425) includes a plurality of second logic blocks (505) which may be programmably coupled using a second programmable interconnect network (521). The second programmable interconnect network (521) may be programmably coupled to the first programmable interconnect network (511).

Abstract: A software driven emulator has a maintenance bus operating protocol mode in which, after an initial address phase, data is streamed continuously by automatically incrementing the sending and receiving addresses.

Abstract: A system for physical emulation of electronic circuits or systems includes a data entry workstation where a user may input data representing the circuit or system configuration. This data is converted to a form suitable for programming an array of programmable gate elements provided with a richly interconnected architecture. Provision is made for externally connecting VLSI devices or other portions of a user's circuit or system a network of internal probing interconnections is made available by utilization of unused circuit paths in the programmable gate arrays.

Abstract: A hardware emulator chip contains an array of cells and a programmable interconnection array. Each cell performs only a single logic function, which is configurable. The chips run asynchronously to one another, and within each chip cells are enabled by a sequential wave signal, which enables successive logical rows of cells. Within the chip, it is possible to connect any arbitrary cell output to any arbitrary cell input. Preferably, a set of off-chip connections is made possible by time-multiplexing the output of each subset to the wave signal. In one embodiment, full interconnection of cells within a chip is provided by providing a time-multiplexed programmable array of interconnect switches, the setting of each switch changing with each successive wave. In a second embodiment, full interconnection of cells within a chip is provided by providing a programmable array of interconnect switches.

Abstract: A hardware design emulation system that includes one or more emulators and one or more associated run-time assist units (RTAUs). The emulator logic is a combination of user model logic, reflecting the hardware design, and non-user model logic. A handshaking controller produces a domain step signal and a model step signal. The domain step signal indicates that the emulator is entering a state for executing the next step of the logic with which it is programmed, be it user model logic or non-user model logic. The model step signal indicates that the emulator is entering a state for advancing the user model defined by the user model logic. This dual handshaking protocol enhances versatility by enabling a wide variety of RTAUs to be used, particularly in combination with one another.

Abstract: A method and apparatus for debugging circuit designs having random access memory therein. The circuit design is emulated on a hardware logic emulator. The RAM emulated by the emulator can be rewound to a previous state, and then replayed. The RAM emulated by the emulator can also be reconstructed to a state the RAM maintained at some point during a trace window.

Abstract: A design verification system utilizing programmable logic devices having varying numbers of logic processors, macro processors, memory processors and general purpose processors programmed therein is disclosed. These various processors can execute Boolean functions, macro operations, memory operations, and other computer instructions. This avoids either the need to implement logic or the need to compile the design into many gate-level Boolean logic operations for logic processors. Improved efficiency in the form of lower cost, lower power and/or higher speeds are the result when verifying certain types of designs.

Abstract: A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common I/O pins and circuit board traces. A logic analyzer for a hardware emulation system is also disclosed. The logic circuits necessary for executing logic analyzer functions is programmed into the programmable resources in the logic chips of the emulation system.

Abstract: This invention features a method of simultaneously conducting simulation testing of a plurality of simulated device designs using cycle-based software which is capable of simultaneously executing a number of simulation tests along separate test pathways for each simulated device. The method is appropriate for situations in which the simulated device designs each comprise essentially identical sequences of boolean instructions. The method contemplates designating a single bit location of a multiple-word memory device for each test of each simulated device. As the test progress, the results of each test are stored in the appropriate designated bit location for such test. This allows a total number of simultaneous tests equal to the number of bits available in the words making up the memory of the memory device.

Abstract: A circuit for an emulation system that has a logic element having a RAM, lookup table, optional delay element and flip-flop/latch. The flip-flop/latch may behave as a flip-flop or as a latch and has separate set and reset signals. The delay element inserts a selectable amount of delay into the data path of the logic element in order to reduce race time problems. The logic elements may be combined to share input signals so as to increase the size of the RAM. The improved circuit also has a playback memory used to store up to a a plurality of copies of sampled data from a logic element so that emulation data can be played back for debugging purposes. Multiple read ports coupled to the logic elements permit a user to read out data from the logic elements during emulation in a time multiplexed manner. The input/output pins may be time multiplexed to carry multiple signals, unidirectionally or bidirectionally.

Abstract: A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common input/output pins and circuit board traces. A logic analyzer for a hardware emulation system is also disclosed. The logic circuits necessary for executing logic analyzer functions is programmed into the programmable resources in the logic chips of the emulation system. A method for dynamically testing the interconnect between integrated circuits is also disclosed.

Abstract: A method for resynthesizing gated clocks in a clock cone of a logic design having more than one input clock where the logic design will be implemented in a hardware logic emulation system. By resynthesizing the gated clocks, timing in the circuit becomes predictable. In the method, predicting logic that predicts which edges of said at least two input clocks may cause a hold time violation on a gated clock is generated. Then, the outputs from the predicting logic are connected to a gated clock resolution circuit, which outputs the resynthesized clock.

Abstract: Clusters of processors are interconnected as an emulation engine such that processors share input and data stacks, and the setup and storing of results are done in parallel, but the output of one evaluation unit is connected to the input of the next evaluation unit. A set of ‘cascade’ connections provides access to the intermediate values. By tapping intermediate values from one processor, and feeding them to the next, a significant emulation speedup is achieved.

Abstract: A logic chip useful for emulation and prototyping of integrated circuits. The logic chip comprises a plurality of logic elements, which is divided into a plurality of subsets of logic elements. The logic chip further comprises a plurality of first level interconnects. The plurality of first level interconnects interconnect one of the plurality of subsets of logic elements, thereby forming a plurality of first level logical units. The plurality of first level logical units is divided into a plurality of subsets of first level logical units. The logic chip also comprises a plurality of second level interconnects. The second level interconnects interconnect one of the plurality of subsets of first level logic units, thereby forming a plurality of second level logic units. The logic chip also comprises a third level interconnect. The third level interconnect interconnects the plurality of second level logic units, thereby forming a third level logic.

Abstract: A fully synthesizeable Simulation Control Module (SCM) controls and monitors the simulation of a design under test (DUT). A clock generator within the SCM and a Software clock facility residing on the host workstation are responsible for providing the clocks for the DUT. The SCM and the hardware clock facility are dynamically generated at build time to suit the needs of the DUT. They maximize performance by automatically generating clock waveforms for designs containing multiple asynchronous clocks, thereby decreasing the frequency of accelerator-workstation interaction. The software clock facility has the ability to directly drive the DUT and is responsible for managing the simulation time and clock parameters. The SCM is also responsible for monitoring an abort condition such as a trigger to execute an external software model. The SCM and the clock facilities allow the hardware accelerator to efficiently support multiple asynchronous clock domains, execution of external software models and co-simulation.

Abstract: Clusters of processors are interconnected as an emulation engine such that processors share input and data stacks, and the setup and storing of results are done in parallel, but the output of one evaluation unit is connected to the input of the next evaluation unit. A set of ‘cascade’ connections provides access to the intermediate values. By tapping intermediate values from one processor, and feeding them to the next, a significant emulation speedup is achieved.