Patents Assigned to Quickturn Design Systems, Inc.
  • Patent number: 5821773
    Abstract: A logic element for a programmable logic device. The logic element includes a look-up table (400) for implementing logical functions, a programmable delay block (415), a storage block (430) configurable as a latch or a flip-flop, and a diagnostic shadow latch (435). A plurality of inputs (410) to the logic element and complements of these inputs are available to control the secondary functions of the storage block (430).
    Type: Grant
    Filed: September 6, 1995
    Date of Patent: October 13, 1998
    Assignees: Altera Corporation, Quickturn Design Systems, Inc.
    Inventors: Kevin A. Norman, Rakesh H. Patel, Stephen P. Sample, Michael R. Butts
  • Patent number: 5819065
    Abstract: A system and method for emulating memory designs is described. The system includes a time sliced logic emulator. The time sliced logic emulator emulates the functions performed in one cycle of a target design by emulating portions of the functions in a set of time slices. That is, a set of time slices represents a single clock cycle in the target design. The system emulates many different types of memory designs included in the target design. The system includes an emulation memory. The memory designs are mapped to the emulation memory via a programmable address generation block. For a given time slice, the programmable address generation block generates an address that maps all or part of a memory design address to an emulation memory address. The programmable address generation block allows multiple memory designs to be mapped to a single emulation memory and allows a single memory design to be mapped to multiple emulation memories.
    Type: Grant
    Filed: February 6, 1996
    Date of Patent: October 6, 1998
    Assignee: Quickturn Design Systems, Inc.
    Inventors: John E. Chilton, Tony R. Sarno, Ingo Schaefer
  • Patent number: 5812414
    Abstract: A plurality of electronically reconfigurable gate array (ERCGA) logic chips are interconnected via a reconfigurable interconnect, and electronic representations of large digital networks are converted to take temporary actual operating hardware form on the interconnected chips. The reconfigurable interconnect permits the digital network realized on the interconnected chips to be changed at will, making the system well suited for a variety of purposes including simulation, prototyping, execution and computing. The reconfigurable interconnect may comprise a partial crossbar that is formed of ERCGA chips dedicated to interconnection functions, wherein each such interconnect ERCGA is connected to at least one, but not all of the pins of a plurality of the logic chips. Other reconfigurable interconnect topologies are also detailed.
    Type: Grant
    Filed: December 19, 1996
    Date of Patent: September 22, 1998
    Assignee: Quickturn Design Systems, Inc.
    Inventors: Michael R. Butts, Jon A. Batcheller
  • Patent number: 5796623
    Abstract: A plurality of electronically reconfigurable gate array (ERCGA) logic chips are interconnected via a reconfigurable interconnect, and electronic representations of large digital networks are converted to take temporary actual operating hardware form on the interconnected chips. The reconfigurable interconnect permits the digital network realized on the interconnected chips to be changed at will, making the system well suited for a variety of purposes including simulation, prototyping, execution and computing. The reconfigurable interconnect may comprise a partial crossbar that is formed of ERCGA chips dedicated to interconnection functions, wherein each such interconnect ERCGA is connected to at least one, but not all of the pins of a plurality of the logic chips. Other reconfigurable interconnect topologies are also detailed.
    Type: Grant
    Filed: December 19, 1996
    Date of Patent: August 18, 1998
    Assignee: Quickturn Design Systems, Inc.
    Inventors: Michael R. Butts, Jon A. Batcheller
  • Patent number: 5734581
    Abstract: A plurality of electronically reconfigurable gate array (ERCGA) logic chips are interconnected via a reconfigurable interconnect, and electronic representations of large digital networks are converted to take temporary actual operating hardware form on the interconnected chips. The reconfigurable interconnect permits the digital network realized on the interconnected chips to be changed at will, making the system well suited for a variety of purposes including simulation, prototyping, execution and computing. The reconfigurable interconnect may comprise a partial crossbar that is formed of ERCGA chips dedicated to interconnection functions, wherein each such interconnect ERQGA is connected to at least one, but not all of the pins of a plurality of the logic chips. Other reconfigurable interconnect topologies are also detailed.
    Type: Grant
    Filed: December 19, 1996
    Date of Patent: March 31, 1998
    Assignee: Quickturn Design Systems, Inc.
    Inventors: Michael R. Butts, Jon A. Batcheller
  • Patent number: 5715172
    Abstract: A method of identifying potential clock qualifiers in netlist description of an integrated circuit, the netlist comprising logic elements. The method comprises the steps of initializing every net of the netlist to a speed of zero, identifying all potential clock nets so that all signals with a path to a clock source has a speed of one, computing the maximum speed of each output net of each of the logic elements in the netlist, and marking as a potential clock qualifier any net of the netlist that is input to the logic elements in the netlist that is slower than the maximum speed of any net that is input to the logic elements.
    Type: Grant
    Filed: April 26, 1996
    Date of Patent: February 3, 1998
    Assignee: Quickturn Design Systems, Inc.
    Inventor: Ping-San Tzeng
  • Patent number: 5661662
    Abstract: A plurality of electronically reconfigurable gate array (ERCGA) logic chips are interconnected via a reconfigurable interconnect, and electronic representations of large digital networks are converted to take temporary actual operating hardware form on the interconnected chips. The reconfigurable interconnect permits the digital network realized on the interconnected chips to be changed at will, making the system well suited for a variety of purposes including simulation, prototyping, execution and computing. The reconfigurable interconnect may comprise a partial crossbar that is formed of ERCGA chips dedicated to interconnection functions, wherein each such interconnect ERCGA is connected to at least one, but not all of the pins of a plurality of the logic chips. Other reconfigurable interconnect topologies are also detailed.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: August 26, 1997
    Assignee: Quickturn Design Systems, Inc.
    Inventors: Michael R. Butts, Jon A. Batcheller
  • Patent number: 5657241
    Abstract: A plurality of electronically reconfigurable gate array (ERCGA) logic chips are interconnected via a reconfigurable interconnect, and electronic representations of large digital networks are converted to take temporary actual operating hardware form on the interconnected chips. The reconfigurable interconnect permits the digital network realized on the interconnected chips to be changed at will, making the system well suited for a variety of purposes including simulation, prototyping, execution and computing. The reconfigurable interconnect may comprise a partial crossbar that is formed of ERCGA chips dedicated to interconnection functions, wherein each such interconnect ERCGA is connected to at least one, but not all of the pins of a plurality of the logic chips. Other reconfigurable interconnect topologies are also detailed.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: August 12, 1997
    Assignee: Quickturn Design Systems, Inc.
    Inventors: Michael R. Butts, Jon A. Batcheller
  • Patent number: 5649167
    Abstract: A method and a structure for implementing integrated circuit designs into a plurality of clocked and unclocked reprogrammable logic circuits. Software structures analyze the target logic circuit, form clusters, partitions the integrated circuit design and implement the partitions into the clocked and unclocked reprogrammable logic circuits in order to prevent hold time violation artifacts.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: July 15, 1997
    Assignee: Quickturn Design Systems, Inc.
    Inventors: Nang-Ping Chen, Robert J. Ko, Jeong-Tyng Li, Thomas B. Huang, Ming-Yang Wang
  • Patent number: 5644515
    Abstract: A system for physical emulation of electronic circuits or systems includes a data entry workstation where a user may input data representing the circuit or system configuration. This data is converted to a form suitable for programming an array of programmable gate elements provided with a richly interconnected architecture. Provision is made for externally connecting VLSI devices or other portions of a user's circuit or system. A network or internal probing interconnections is made available by utilization of unused circuit paths in the programmable gate arrays.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: July 1, 1997
    Assignee: Quickturn Design Systems, Inc.
    Inventors: Stephen P. Sample, Michael R. D'Amour, Thomas S. Payne
  • Patent number: 5612891
    Abstract: A plurality of electronically reconfigurable gate array (ERCGA) logic chips are interconnected via a reconfigurable interconnect, and electronic representations of large digital networks are converted to take temporary actual operating hardware form on the interconnected chips. The reconfigurable interconnect permits the digital network realized on the interconnected chips to be changed at will, making the system well suited for a variety of purposes including simulation, prototyping, execution and computing. The reconfigurable interconnect may comprise a partial crossbar that is formed of ERCGA chips dedicated to interconnection functions, wherein each such interconnect ERCGA is connected to at least one, but not all of the pins of a plurality of the logic chips. Other reconfigurable interconnect topologies are also detailed.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: March 18, 1997
    Assignee: Quickturn Design Systems, Inc.
    Inventors: Michael R. Butts, Jon A. Batcheller
  • Patent number: 5563829
    Abstract: A method of implementing a multi-port memory circuit in the memory resources of configuration logic blocks of programmable logic devices. The multi-port memory circuit to be implemented comprises a memory array having memory locations for storing data, read ports for reading data from the memory array and write ports for writing data to the memory array. Multiple duplications of the memory array are created in order to implement as many read ports and write ports as the multi-port memory circuit being implemented. The memory locations within the duplicate memory arrays are tagged to indicate which memory location had data written therein last so that only the last written data will be read through the various read ports.
    Type: Grant
    Filed: September 1, 1995
    Date of Patent: October 8, 1996
    Assignee: Quickturn Design Systems, Inc.
    Inventor: Thomas B. Huang
  • Patent number: 5477475
    Abstract: A system for physical emulation of electronic circuits or systems includes a data entry workstation where a user may input data representing the circuit or system configuration. This data is converted to a form suitable for programming an array of programmable gate elements provided with a richly interconnected architecture. Provision is made for externally connecting VLSI devices or other portions of a user's circuit or system. a network of internal probing interconnections is made available by utilization of unused circuit paths in the programmable gate arrays.
    Type: Grant
    Filed: July 11, 1994
    Date of Patent: December 19, 1995
    Assignee: Quickturn Design Systems, Inc.
    Inventors: Stephen P. Sample, Michael R. D'Amour, Thomas S. Payne
  • Patent number: 5475830
    Abstract: A method and a structure for implementing integrated circuit designs into a plurality of clocked and unclocked reprogrammable logic circuits. Software structures analyze the target logic circuit, form clusters, partition the integrated circuit design and implement the partitions into the clocked and unclocked reprogrammable logic circuits in order to prevent hold time violation artifacts.
    Type: Grant
    Filed: January 31, 1992
    Date of Patent: December 12, 1995
    Assignee: Quickturn Design Systems, Inc.
    Inventors: Nang-Ping Chen, Robert J. Ko, Jeong-Tyng Li, Thomas B. Huang, Ming-Yang Wang
  • Patent number: 5452231
    Abstract: A plurality of electronically reconfigurable gate array (ERCGA) logic circuits are interconnected via a reconfigurable interconnect, and electronic representations of large digital networks are converted to take temporary actual operating hardware form on the interconnected circuits. The reconfigurable interconnect permits the digital network realized on the interconnected circuits to be changed at will, making the system well suited for a variety of purposes including simulation, prototyping, execution and computing. The reconfigurable interconnect may comprise a partial crossbar that is formed of ERCGA circuits dedicated to interconnection functions, wherein each such interconnect ERCGA is connected to at least one, but not all of the pins of a plurality of the logic circuits. Other reconfigurable interconnect topologies are also detailed. If desired, the logic circuits and interconnect can be implemented in wafer-scale technology.
    Type: Grant
    Filed: May 17, 1994
    Date of Patent: September 19, 1995
    Assignee: Quickturn Design Systems, Inc.
    Inventors: Michael R. Butts, Jon A. Batcheller
  • Patent number: 5452239
    Abstract: An emulation system and method that reduces or eliminates the number of timing errors such as hold time violations when implementing a netlist description of an integrated circuit. The emulation system comprises a plurality of reprogrammable logic circuits and a plurality of reprogrammable interconnect circuits. The netlist description is optimized to reduce the number of timing violations by removing the occurences of gated clocks from the netlist, partitioning the netlist description by taking into account the occurence of timing violations and ensuring that retain state nets are implemented properly.
    Type: Grant
    Filed: February 26, 1993
    Date of Patent: September 19, 1995
    Assignee: Quickturn Design Systems, Inc.
    Inventors: Wei-Jin Dai, Louis Galbiati, III, Joseph Varghese, Dam V. Bui, Stephen P. Sample
  • Patent number: 5448496
    Abstract: A plurality of electronically reconfigurable gate array (ERCGA) logic chips are interconnected via a reconfigurable interconnect, and electronic representations of large digital networks are converted to take temporary actual operating hardware form on the interconnected chips. The reconfigurable interconnect permits the digital network realized on the interconnected chips to be changed at will, making the system well suited for a variety of purposes including simulation, prototyping, execution and computing. The reconfigurable interconnect may comprise a partial crossbar that is formed of ERCGA chips dedicated to interconnection functions, wherein each such interconnect ERCGA is connected to at least one, but not all of the pins of a plurality of the logic chips. Other reconfigurable interconnect topologies are also detailed.
    Type: Grant
    Filed: July 1, 1994
    Date of Patent: September 5, 1995
    Assignee: Quickturn Design Systems, Inc.
    Inventors: Michael R. Butts, Jon A. Batcheller
  • Patent number: 5448522
    Abstract: A method of implementing a multi-port memory circuit in the memory resources of configuration logic blocks of programmable logic devices. The multi-port memory circuit to be implemented comprises a memory array having memory locations for storing data, read ports for reading data from the memory array and write ports for writing data to the memory array. Multiple duplications of the memory array are created in order to implement as many read ports and write ports as the multi-port memory circuit being implemented. The memory locations within the duplicate memory arrays are tagged to indicate which memory location had data written therein last so that only the last written data will be read through the various read ports.
    Type: Grant
    Filed: March 24, 1994
    Date of Patent: September 5, 1995
    Assignee: Quickturn Design Systems, Inc.
    Inventor: Thomas B. Huang
  • Patent number: 5425036
    Abstract: An improved electronic design automation (EDA) system employs field programmable gate arrays (FPGAs) for emulating prototype circuit designs. A circuit netlist file is down-loaded to the FPGAs to configure the FPGAs to emulate a functional representation of the prototype circuit. To check whether the circuit netlist is implemented properly, the FPGAs are tested functionally by applying input vectors thereto and comparing the resulting output of the FPGAs to output vectors provided from prior simulation. If the FPGAs fail such vector comparison, the FPGAs are debugged by inserting "read-back" trigger instructions in the input vectors, preferably corresponding to fail points in the applied vector stream. Modifying the input vectors with such read-back signals causes the internal states of latches and flip-flops in each FPGA to be captured when functional testing is repeated.
    Type: Grant
    Filed: September 18, 1992
    Date of Patent: June 13, 1995
    Assignee: Quickturn Design Systems, Inc.
    Inventors: Dick L. Liu, Jeong-Tyng Li, Thomas B. Huang, Kenneth S. K. Choi