Abstract: An overcurrent protection circuit for input/Output (I/O) buffers for a Field Programmable Gate Array wherein short circuits can be detected and the output current limited so as to avoid damaging the device. I/O buffers having the overcurrent protection circuit can detect a contention between the buffers. In order to eliminate the contention, certain I/O buffers will go into a noncontending state.

Abstract: An integrated circuit for implementing reconfigurable logic, such as a field programmable gate array ("FPGA"), as described herein has flexible input/output buffer circuits. These input/output buffer circuits transfer data either bidirectionally or unidirectionally between an input/output pin and a FPGA core. Each input/output buffer circuit allows at least two signals to be time-multiplexed onto an input/output pin thereby doubling the effective input/output capacity. The input/output buffer circuits may be used to time-multiplex at least two signals onto an input pin, at least two signals onto an output pin, or both. Each input/output buffer circuit further has shared flip flops for time-multiplexing signals. The circuitry provides two connections into the FPGA core which can be used to time-multiplex at least two independent inputs or outputs.

Abstract: An integrated circuit for implementing reconfigurable logic, such as a field programmable gate array ("FPGA"), as described herein has multiple blocks of multi-ported memory. The memory has a plurality of read ports and a plurality of write ports. Each port of the multi-ported memory can be configured with a width and depth that is independent and separate from the width and depth of the other ports. The memory also includes a port for taking a synchronous snapshot of the contents of the memory or for loading the memory to an initial state. The memory shares routing lines used by a low level logic element thereby alleviating the need to add routing lines to an interconnect network just to satisfy the memory requirements.

Abstract: A plurality of electronically reconfigurable gate array (ERCGA) logic chips are interconnected via a reconfigurable interconnect, and electronic representations of large digital networks are converted to take temporary actual operating hardware form on the interconnected chips. The reconfigurable interconnect permits the digital network realized on the interconnected chips to be changed at will, making the system well suited for a variety of purposes including simulation, prototyping, execution and computing. The reconfigurable interconnect may comprise a partial crossbar that is formed of ERCGA chips dedicated to interconnection functions, wherein each such interconnect ERCGA is connected to at least one, but not all of the pins of a plurality of the logic chips. Other reconfigurable interconnect topologies are also detailed.

Abstract: A configurable method and apparatus for implementing the various large memory instances commonly found in a user's design in a hardware logic emulation system is disclosed. No external boards or systems are required to implement typical memory instances. The method and apparatus sorts the memory instances in the user's input design, packing as many memory instances as possible into a physical RAM on the emulation boards. The method also counts the number of physical RAMs necessary to implement the plurality of memory instances. The method maps the memory instances into physical RAMs, and routes the address, data and control signals and controller circuit into a programmable logic chip.

Abstract: A time-sliced hardware-based emulator including at least one of: programmable I/O assignment; programmable levels of DC voltage; programmable pull-up or pull-down resistors in the emulator on a pin-by pin basis; programmable forcing and/or disabling of value output from the emulator on each pin; programmable clocking; and programmable sample modes. An emulator is connected to a target system via a Pod System Interface (PSI), a specially designed cable, and a Pod User Interface (PUI). For data traveling from the emulator to the target system, each PSI receives up to 128 bits of data from the emulator. The cable, however, is only 32 bits wide. Therefore, the emulator multiplexes the data sent over the cable, sending eight interleaved groups of 32 bits to the PSI in accordance with a fast clock signal. Each PUI receives the groups of 32 bits from the PSI and sends them to the target system in accordance with control signals from the emulator.

Abstract: A system for physical emulation of electronic circuits or systems includes a data entry workstation where a user may input data representing the circuit or system configuration. This data is converted to a form suitable for programming an array of programmable gate elements provided with a richly interconnected architecture. Provision is made for externally connecting VLSI devices or other portions of a user's circuit or system. A network or internal probing interconnections is made available by utilization of unused circuit paths in the programmable gate arrays.

Abstract: A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common I/O pins and circuit board traces. A logic analyzer for a hardware emulation system is also disclosed. The logic circuits necessary for executing logic analyzer functions is programmed into the programmable resources in the logic chips of the emulation system.

Abstract: A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common I/O pins and circuit board traces. A logic analyzer for a hardware emulation system is also disclosed. The logic circuits necessary for executing logic analyzer functions is programmed into the programmable resources in the logic chips of the emulation system.

Abstract: A memory design is implemented in static memory circuits having a plurality of bidirectional access ports, wherein each port is configured for read or write access. The memory design defines initial contents, depth, width, and bank selection in the memory circuits according to predefined configuration values, as well as, for each access port, whether that access port is configured for read or write. Port access occurs during time slots, which are based on external clock signals and memory circuit access times. Modified memory designs may be implemented such that access ports are accordingly reconfigured.

Abstract: A logic emulation system for emulating the operation of a circuit. A uniform routing architecture is provided where a first set of selectors (multiplexers) is coupled to a set of shift registers that are in turn coupled to a second set of selectors. The outputs of the second set of selectors are coupled to the inputs of the logic processors. The arrangement of first selectors coupled to shift registers coupled to second selectors coupled to logic processors ensures that uniform routing exists among all of the logic processors in the emulation system. This, in turn, provides a flat programming model so that compilation steps including technology mapping and scheduling are independent of each other, resulting in faster compile times.

Abstract: An emulator system allowing a single cycle in a system clock in a user circuit to be emulated in multiple cycles of the emulator system clock. The emulator system provides a unique architecture permitting gates in the emulator to be used to emulate functions in the user circuit without requiring a fixed correspondence between a gate in the emulator and a gate in the user circuit. The emulator system operates in synchronous and asynchronous clock modes and allows the user system clock to be stopped during emulation in selected modes while still maintaining accurate emulation.

Abstract: A physical interconnection architecture for making connections between a plurality of first printed-circuit boards and a plurality of second printed-circuit boards includes a midplane printed-circuit board having a plurality of first connectors oriented in a first direction on one side of the midplane for making connections to the plurality of first printed-circuit boards. The midplane printed-circuit board also has a plurality of second connectors oriented in a second direction orthogonal to the plurality of first connectors on the other side of the midplane. The connectors are positioned such that connection pins on the plurality of first connectors and plurality of second connectors in regions of intersection are double-ended pins common to both. The remaining connection pins of the plurality of first connectors are single-ended connection pins which are connected to the single-ended connection pins of the plurality of second connectors via conductive traces on the midplane printed-circuit board.

Abstract: A method for optimizing a logical design for emulation. The present invention optimzes latch-based designs by transforming them into a flip-flop based circuit. The design is analyzed to determine whether any consecutive latches are clocked by the same clock signal. If consecutive latches are clocked by the same clock signal, for example, the same phase of the same master clock, a transparency condition exists. Transparent latches are transformed into either a flip-flop/buffer/multiplexer circuit or a buffer circuit depending upon whether the latch in the logic design has an enable input. If consecutive latches in a design are clocked by different clock signals, i.e., different phases of the master clock, no transparency condition exists. Non-transparent latches are transformed into a flip-flop.

Abstract: A tracing method and apparatus for a digital emulation system. The invention allows trace information to be obtained during the emulation of a digital circuit that includes a clock signal. Input signal states are sensed and stored each clock cycle. The internal state of the emulated digital circuit is also stored. By using the stored input signal states and internal states, the states of other signals in the emulated digital circuit are derived.

Abstract: An diagnostic interface system for a programmable logic system is disclosed. The diagnostic interface system provides an efficient and flexible mechanism for accessing internal nodes of programmable logic devices (PLDs) to facilitate debugging and troubleshooting of the programmable logic system. The interface system includes a diagnostic data bus connecting external I/O pins to various diagnostic data and address registers that connect to the internal circuitry of a PLD. A diagnostics controller controls the various diagnostic resources in response to user supplied control data.

Abstract: Methods of speeding error analysis of electronic devices under test using simulation software that has the capability of simultaneously executing up to 32 tests on one image of the design model. One embodiment of the method contemplates executing the tests staggered in time so that a larger portion of the test is available for examination and execution at any given time. This allows errors to be found more quickly. Another embodiment contemplates more quickly testing a device initialization sequence by randomly establishing values for each state device, separately for each of the 32 tests, running the simulation, and then determining whether the state device values converge.

Abstract: A method and apparatus for combining emulation and simulation of a logic design. The method and apparatus can be used with a logic design that includes gate-level descriptions, behavioral representations, structural representations, or a combination thereof. The emulation and simulation portions are combined in a manner that minimizes the time for transferring data between the two portions. Simulation is performed by one or more microprocessors while emulation is performed in reconfigurable hardware such as field programmable gate arrays. When multiple microprocessors are employed, independent portions of the logic design are selected to be executed on the multiple synchronized microprocessors. Reconfigurable hardware also performs event detecting and scheduling operations to aid the simulation, and to reduce processing time.

Abstract: A method and a structure provide emulation circuit implemented on a logic block module comprising clocked and unclocked field programmable logic devices (FPGAs). Software modules analyze the target logic circuit and impose delay constraints to require certain storage instances to be implemented on separate FPGAs so as to prevent hold time violation artifacts.

Abstract: A logic element for a programmable logic device. The logic element includes a look-up table (400) for implementing logical functions, a programmable delay block (415), a storage block (430) configurable as a latch or a flip-flop, and a diagnostic shadow latch (435). A plurality of inputs (410) to the logic element and complements of these inputs are available to control the secondary functions of the storage block (430).