Abstract: A transceiver includes a transmitter and receiver that form a series current path between two power-supply nodes. Powering both the transmitter and receiver with the same supply current saves power. The transmitter functions as a resistive load for the receiver, and thus performs useful work with power that would otherwise be dissipated as waste heat.

Abstract: During an exposure interval within an integrated-circuit image sensor, a first sequence of sample values, obtained by iteratively sampling a first pixel, is accumulated within a counter. The counter is reset to clear the first count value, and then a second sequence of sample values, obtained by iteratively sampling a second pixel, is accumulated within the counter.

Abstract: A dynamic random access memory (DRAM) array is configured for selective repair and error correction of a subset of the array. Error-correcting code (ECC) is provided to a selected subset of the array to protect a row or partial row of memory cells where one or more weak memory cells are detected. By adding a sense amplifier stripe to the edge of the memory array, the adjacent edge segment of the array is employed to store ECC information associated with the protected subsets of the array. Bit replacement is also applied to defective memory cells. By implementing ECC selectively rather than to the entire array, integrity of the memory array is maintained at minimal cost to the array in terms of area and energy consumption.

Abstract: An LED lamp or LED lighting assembly includes a light guide having opposed major surfaces configured to propagate light by total internal reflection and a light input edge extending between the major surfaces. A light source is adjacent to the light input edge and is configured to edge light the light guide. In some embodiments, the light source is moveable relative to the light input edge, and the spectrum of the light output from the light guide may be adjusted by movement of the light source relative to the light input edge.

Abstract: A memory module comprises a module interface having module data-group ports to communicate data as respective data groups, a command port to receive memory-access commands, a first memory device including a first device data-group port, a second memory device including a second device data-group port, and a signal buffer coupled between the module interface and each of the first and second devices. In a first mode, in response to the memory-access commands, the signal buffer communicates the data group associated with each of the first and second device data-group ports via a respective one of the module data-group ports. In a second mode, in response to the memory-access commands, the signal buffer alternatively communicates the data group associated with the first device data-group port or the data group associated with the second device data-group port via the same one of the module data-group ports.

Abstract: A signaling system is described. The signaling system comprises a transmit device, a receive device including a partial response receive circuit, and a signaling path coupling the transmit device and the receive device. The receive device observes an equalized signal from the signaling path, and includes circuitry to use feedback from the most recent previously resolved symbol to sample a currently incoming symbol. The transmit device equalizes transmit data to transmit the equalized signal, by applying weighting based on one or more data values not associated with the most recent previously resolved symbol value.

Abstract: A device includes a first interface to receive a signal from a first communication link, wherein the receive signal includes out-of-band (OOB) information. A detector coupled to the first interface detects the OOB information. An encoder coupled to the detector encodes the OOB information into one or more symbols (e.g., control characters). A second interface is coupled to the encoder and a second communication link (e.g., a serial transport path). The second interface transmits the symbols on the second communication link. The device also includes mechanisms for preventing false presence detection of terminating devices.

Abstract: Clocking systems and methods are provided below that accurately clock per-pin data transfers of input/output (IO) circuits of integrated circuit devices. These multiplexer-based clock selection systems use a dedicated multiplexer to receive clock signals from multiple mixer circuits and in turn to provide a selected reference clock signal for use by an interface circuit in transferring data to other integrated circuit devices. The timing of the selected reference clock signal is synchronized with the data signals to provide optimal sampling of the data signals. The multiplexer-based clock selection system is for use in memory interfaces of high-speed signaling systems for example.

Abstract: Components of a memory system, such as a memory controller and a memory device, that reduce delay in exiting self-refresh mode by controlling the refresh timing of the memory device. The memory device includes a memory core. An interface circuit of the memory device receives an external refresh signal indicating an intermittent refresh event. A refresh circuit of the memory device generates an internal refresh signal indicating an internal refresh event of the memory device. A refresh control circuit of the memory device performs a refresh operation on a portion of the memory core responsive to the internal refresh event, at a time relative to the intermittent refresh event indicated by the external refresh signal.

Abstract: A memory system includes a memory controller that writes data to and reads data from a memory device. A write data strobe accompanying the write data indicates to the memory device when the write data is valid, whereas a read strobe accompanying data from the memory device indicates to the memory controller when the read data is valid. The memory controller adaptively controls the phase of the write data strobe to compensate for timing drift at the memory device. The memory controller uses read signals as a measure of the drift.

Abstract: A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.

Abstract: An integrated circuit device is disclosed. The integrated circuit device includes a semiconductor die fabricated by a front-end semiconductor process and having oppositely disposed planar surfaces. The semiconductor die is formed with semiconductor devices, power supply circuitry coupled to the semiconductor devices, decoupling capacitance circuitry, and through-vias. The through-vias include a first group of vias coupled to the power supply circuitry and a second group of vias coupled to the decoupling capacitance circuitry. Conductors are formed in a first metal layer disposed on the semiconductor die in accordance with a back-end semiconductor process. The conductors are configured to couple to the first and second groups of through-vias to establish conductive paths from the power supply circuitry to the decoupling capacitance circuitry.

Abstract: A lighting assembly includes a light guide having a first major surface, a second major surface opposite the first major surface, a light input edge, and an end edge distal the light input edge. Light input to the light guide through the light input edge propagates by total internal reflection toward the end edge. The lighting assembly further includes light extracting elements at least one of the major surfaces of the light guide, the light extracting elements configured to extract light through the first major surface in a direction away from the light input edge and away from the first major surface, and a banding reduction element at the end edge configured to redirect light incident thereon in a direction away from the light input edge.

Abstract: A light bulb includes a base, light guide, and light source. The base is configured to mechanically mount the light bulb and receive electrical power. The light guide includes light input regions, at least one of the light input regions associated with an optical modifying characteristic, the light guide configured to propagate light by total internal reflection. The light source is located adjacent the light input regions. The light source and light input regions are variably positionable relative to one another to vary location at which light is incident on the light input regions such that light emitted from the light source is selectively apportioned between the light input regions. A characteristic of the light output from the light bulb is modified based on the optical modifying characteristic of the at least one of the light input regions and the relative positioning of the light source and light input regions.

Abstract: A high-speed signaling system with adaptive transmit pre-emphasis. A transmit circuit has a plurality of output drivers to output a first signal onto a signal path. A receive circuit is coupled to receive the first signal via the signal path and configured to generate an indication of whether the first signal exceeds a threshold level. A first threshold control circuit is coupled to receive the indication from the receive circuit and configured to adjust the threshold level according to whether the first signal exceeds the threshold level. A drive strength control circuit is coupled to receive the indication from the receive circuit and configured to adjust a drive strength of at least one output driver of the plurality of output drivers according to whether the first signal exceeds the threshold level.

Abstract: In a pixel array within an integrated-circuit image sensor, each of a plurality of pixels is evaluated to determine whether charge integrated within the pixel in response to incident light exceeds a first threshold. N-bit digital samples corresponding to the charge integrated within at least a subset of the plurality of pixels are generated, and then applied to a lookup table to retrieve respective M-bit digital values (M being less than N), wherein a stepwise range of charge integration levels represented by possible states of the M-bit digital values extends upward from a starting charge integration level that is determined based on the first threshold.

Abstract: In an image sensor pixels in an array of binary pixels are sampled with a first oversampling factor during a first frame interval, and then sampled with a second oversampling factor during a second frame interval, the second oversampling factor exceeding the first oversampling factor.

Abstract: A memory system includes wordlines and pairs of complementary bitlines that provide access to memory storage elements. Capacitive and resistive loads associated with wordlines and bitlines are driven relatively slowly between voltage levels to reduce peak current, and thus power dissipation. Power dissipation is further reduced by charging complementary bitlines at substantially different rates.

Abstract: A clock recovery circuit includes a first phase detector for measuring the phase difference between a first clock signal from a voltage controlled oscillator (VCO) and a data signal. A phase shifter responsive to a control signal based on this phase difference adjusts the phase of an incoming clock signal to yield a second clock signal. The phase difference between the first clock signal and the second clock signal is measured and the resulting signal is low-pass filtered to derive a control signal for controlling the VCO. The phase locked loop including the VCO filters out jitter.