Abstract: A method for improving data retention in a 2T/2C ferroelectric memory includes baking a ferroelectric memory configured to operate as an array of 1T/1C memory cells for a period of time, and then configuring the ferroelectric memory to function as an array of 2T/2C memory cells, wherein the baking pre-imprints the ferroelectric capacitors in the ferroelectric memory and stabilizes a 2T/2C opposite state margin and enhances data retention. A corresponding memory circuit for configuring an array of memory cells for either 1T/1C operation or 2T/2C operation includes a plurality of sense amplifiers, a configurable reference circuit coupled to a logic circuit, a memory array, and a column decoder, wherein components are coupled together through a bit line and a complementary bit line, and wherein the logic circuit can configure the reference circuit for 1T/1C operation or 2T/2C operation.

Abstract: A method of encapsulating a ferroelectric capacitor or ferroelectric memory cell includes forming encapsulation materials adjacent to a ferroelectric capacitor. forming a ferroelectric oxide (FEO) layer over the encapsulated ferroelectric capacitor, and forming an FEO encapsulation layer over the ferroelectric oxide to provide additional protection from hydrogen induced degradation.

Abstract: A delay circuit for an RFID tag includes a power supply input and a power supply output and one or more delay circuits in cascade connection between the power supply input and the power supply output. A first delay circuit includes a passive circuit, a second delay circuit includes a ramp circuit, and a third delay circuit includes a current mirror circuit.

Abstract: Disclosed is a non-volatile, ferroelectric random access memory (F-RAM) device and a method for fabricating the same in the form of a damascene self-aligned F-RAM device comprising a PZT capacitor built on the sidewalls of an oxide trench, while allowing for the simultaneous formation of two ferroelectric sidewall capacitors.

Abstract: Disclosed is a non-volatile, ferroelectric random access memory (F-RAM) device and a method for fabricating a damascene self-aligned F-RAM that allows for the formation of a ferroelectric capacitor with separated PZT layers aligned with a preexisting, three dimensional (3-D) transistor structure.

Abstract: Disclosed is a novel non-volatile, ferroelectric random access memory (F-RAM) device and a method for fabricating a damascene self-aligned F-RAM device structure on a planar surface using a reduced number of masks and etching steps.

Abstract: Sequencing circuitry for a ferroelectric RFID circuit includes an input node for receiving an external voltage, a bandgap circuit coupled to the input node, a bandgap ready circuit coupled to the bandgap circuit, a slew filter having an input coupled to the input node and to the bandgap ready circuit, a filter capacitor coupled to an output of the slew filter, and an LDO regulator having an input coupled to the output of the slew filter having a plurality of regulated voltages for use in a memory portion, a digital circuit portion, and for generating a reset signal. The sequencing circuitry further includes delay circuits for introducing a controlled delay between operational modes, POR cells for monitoring power supply voltages, and a digital state machine for monitoring internal nodes to control a shut-down pulse generator.

Abstract: A bandgap ready circuit for an RFID tag includes a bandgap circuit for providing a bandgap voltage, a first comparator for monitoring first and second voltages in the bandgap circuit and for providing a first logic signal, a second comparator for monitoring third and fourth voltages in the bandgap circuit and for providing a second logic signal, and a logic circuit for combining the first and second logic signals to provide a bandgap ready logic signal.

Abstract: A dynamic adjusting RFID demodulator circuit includes an envelope detector having an input for receiving a modulated RF signal, a fixed reference generator coupled to the input of an RC filter, an RF level dependent signal path adding to the fixed reference level at higher RF energy levels, a comparator having a first input coupled to an output of the envelope detector, a second input coupled to an output of the RC filter, and an output for providing a data output signal.

Abstract: A clamp circuit for an RFID tag includes a power supply node, a dynamic clamp coupled between the power supply node and ground, and an active clamp coupled between the power supply and ground, having a shunt combined effect for providing a clamped power supply node VDDR voltage. The dynamic clamp includes a capacitor divider circuit, a resistor coupled to the capacitor divider circuit, and an N-channel transistor coupled to the capacitor divider circuit. The active clamp includes a differential amplifier having a first input coupled to a resistor divider, a second input for receiving a reference voltage, and an output coupled to a P-channel transistor for the clamped VDDR voltage.

Abstract: A voltage regulator for low power operation of digital circuits includes an output node for providing a regulated output voltage, a diode-connected P-channel transistor in series with a second diode-connected N-channel transistor coupled between the output node and ground, and a bias current having a value for biasing the first and second diode-connected transistors in a sub-threshold mode of operation. The low power voltage regulator further includes a buffer amplifier or emitter or source follower stage to provide a low impedance regulated voltage. The bias current may be generated by a bandgap circuit.

Abstract: A shunt regulator for an RFID tag chip is powered from split outputs from the RF rectifier, including a first output for providing a power delivery path to on-chip circuits and a second output for providing a discharge-regulation path. The shunt regulator includes a capacitor coupled between the first output and ground. The shunt regulator further includes an input node for receiving a power supply voltage from the rectifier split outputs, a first diode having an anode coupled to the input node, a second diode having an anode coupled to the input node, a resistor divider circuit and amplifier coupled between a cathode of the first diode and ground, transistor having a control terminal coupled to an output of the resistor divider and amplifier circuit, and a current path coupled between a cathode of the second diode and ground.

Abstract: A stack processor using a ferroelectric random access memory (F-RAM) for both code and data space which presents the advantages of easy stack pointer management inasmuch as the stack pointer is itself a memory address. Further, the time for saving all critical registers to memory is also minimized in that all registers are already maintained in non-volatile F-RAM per se.

Abstract: A stack processor using a ferroelectric random access memory (F-RAM) for code space and a portion of the stack memory space. By storing some of the associated stacks in complementary metal oxide semiconductor (CMOS) or other volatile memory, read/write operations to only F-RAM would be obviated. As compared to an all F-RAM stack implementation, a faster, less power consuming and faster program execution time is provided. Firmware code can also be provided that will tend to concentrate the more intensive calculations to that part of the stack that is in volatile memory and minimize POP/PUSH operations to the F-RAM portion of the stack. Moreover, since only the top of the stack is maintained in volatile memory, most of it remains in F-RAM which means the application can still benefit from the high F-RAM endurance and shorter power-down times.

Abstract: A stack processor and method implemented using a ferroelectric random access memory (F-RAM) for code and a portion of the stack memory space having an instruction set optimized to minimize processor stack accesses and thus minimize program execution time. This is particularly advantageous in low power applications and those in which the power supply is only available for a finite period of time such as RFID implementations. Disclosed herein is a relatively small but complete set of instructions enabling a multitude of possible applications to be supported with a program execution time that is not too long.

Abstract: A stack processor using a non-volatile, ferroelectric random access memory (F-RAM) for both code and data space. The stack processor is operative in response to as many as 64 possible instructions based upon a 16 bit word. Each of the instructions in the 16 bit word comprises 3 five bit instructions and a 16th bit which is applicable to each of the 3 five bit instructions thereby making each instruction effectively 6 bits wide.

Abstract: An F-RAM authenticating memory device and method providing secure mutual authentication between a Host system and a memory in order to gain read/write access to the F-RAM user memory contents. The device and technique of the present invention uses an Advanced Encryption Standard AES128 encryption module in conjunction with a true hardware random number generator and basic exclusive OR (XOR) functions in order to achieve a secure algorithm with a relatively small amount of processing. Due to inherently faster write times than that of conventional floating gate non-volatile memory technologies, the use of F-RAM significantly reduces the time available to interfere with a critical security parameter (CSP) update. Moreover, unlike floating gate technologies, F-RAM's read vs. write current signature is balanced making it less prone to side channel attacks while also providing relatively faster erase times.

Abstract: A method of operating a memory in an RFID application includes locating a memory pointer at a fixed read/writeable memory location in the memory, determining a range of a pedigree buffer, initializing the memory pointer to a lowest value in the range, providing a second memory location that serves as a trigger address for an indirect write, and writing to a next location in the pedigree buffer by directing write data to the trigger address, which is then automatically written at a location pointed to by the memory pointer.

Abstract: A memory circuit includes a memory, a memory access control circuit coupled to the memory, an RFID interface coupled to the memory access control circuit, a secondary interface coupled to the memory access control circuit, and an interrupt manager coupled to the memory access control circuit, the RFID interface, and the secondary interface.

Abstract: A serial interface includes a select node, a clock node, a first bidirectional data port, a second bidirectional data port, and shift register circuitry coupled to both data ports such that a leading edge and a falling edge of a clock signal associated with the clock node are used to shift or transfer data.