Abstract: A capacitance sensing technique for ferroelectric random access, memory devices and arrays which enables fast sensing operations to be performed allowing for low latency “read” operations and thereby providing overall system performance advantages. Through the use of the technique of the disclosed, concurrent polling and reading of data may be achieved prior to pulsing (or driving) the plate line. This then allows the memory “restore” function to be hidden behind the “read” data stream at the memory device output pins. In accordance with the technique of the present invention, the sensing may begin prior to pulsing the plate line and it is the sensing process itself which interrogates the memory and concurrently prepares the data for the outputs. In this manner, it is the pulsing of the plate line after the data is sensed that performs the “restore” and this operation is not a portion of the “read” access time critical path.

Abstract: Various logic elements such as SR flip-flops, JK flip-flops, D-type flip-flops, master-slave flip-flops, parallel and serial shift registers, and the like are converted into non-volatile logic elements capable of retaining a current output logic state even though external power is removed or interrupted through the strategic addition of ferroelectric capacitors and supporting circuitry. In each case, the building blocks of a cross-coupled sense amplifier are identified within the logic element and the basic cell is modified and/or optimized for sensing performance.

Abstract: A hydrogen barrier encapsulation technique for the control of hydrogen induced degradation of ferroelectric capacitors in non-volatile integrated circuit memory devices. The resultant device structure ameliorates the hydrogen induced degradation of ferroelectric capacitors by completely encapsulating the capacitor within a suitable hydrogen barrier material, such as chemical vapor deposition (“CVD”) or sputtered silicon nitride, thus ensuring process compatibility with industry standard process steps. Although the deposition process for CVD Si3N4 itself contains hydrogen, the deposition time may be kept relatively short thereby allowing the TiN local interconnect layer to act as a “short term” hydrogen barrier.

Abstract: A ferroelectric memory cell includes a ferroelectric capacitor including a bottom electrode, a ferroelectric layer formed on the bottom electrode and a top electrode formed on the ferroelectric layer, a high permittivity dielectric layer formed over the ferroelectric capacitor, wherein the high permittivity dielectric layer includes an encapsulation layer and completely covers the top electrode, and a local interconnect electrode formed on the encapsulation layer.

Abstract: A memory cell layout for use in a 1T/1C ferroelectric memory array includes an access transistor having a gate coupled to a word line and a current path coupled between a bit line and an internal cell node, a shunt word line extending across the memory cell that is electrically isolated from the word line and the access transistor within the physical boundary of the memory cell, and a ferroelectric capacitor coupled between the internal cell node and a plate line.

Abstract: A method of generating an information signal in a 1T/1C, ferroelectric memory cell where the bit line and plate line are arranged parallel to one another is described. The method includes precharging the bit line to a voltage VDD while the plate line is set to ground when a word line is selected. A semiconductor memory device is also described that has an array of 1T/1C memory cells arranged in a bit-plate parallel architecture, where a plurality of adjacent memory cells that share a common plate line are read or written to simultaneously.

Abstract: A low voltage boost circuit suitable for use in a ferroelectric memory is realized implementing five N-channel devices and two ferroelectric capacitors. The voltage on a word line is boosted using charge sharing techniques in order to assure proper operation at lower power supply voltage conditions. In operation, the gate of an N-channel pass gate is boosted to supply a full VDD voltage on the bottom electrode of a ferroelectric capacitor, which capacitively couples into the word line for an efficient word line voltage boost.

Abstract: A method for fabricating integrated capacitors, of particular utility in forming a ferroelectric capacitor array for a ferroelectric memory integrated circuits, begins with provision of a substrate. The substrate is typically a partially-processed CMOS integrated circuit wafer coated with an adhesion layer. Upon the substrate is deposited a bottom electrode layer, typically of noble metal, a dielectric layer, typically doped PZT, and a top electrode layer, typically a noble metal oxide. Next is deposited a hardmask layer of strontium ruthenium oxide, followed by a photoresist layer. The photoresist layer is aligned, exposed, developed, and cured as known in the art of integrated circuit photolithography. The resulting stack is then dry etched to remove undesired portions of the hardmask layer, the top electrode layer, and the dielectric layer. A principle advantage of the process is that a single photomasking operation is sufficient to define the top electrode and dielectric layers.

Abstract: A charge storage capacitor includes a bottom electrode, a dielectric layer formed on the bottom electrode, and a local interconnect electrode formed on the dielectric layer, wherein the dielectric layer is an encapsulation layer, and a ferroelectric memory cell includes the charge storage capacitor.

Abstract: An implementation of 1T/1C nonvolatile ferroelectric RAMS without using any reference cells—the polarization state in a memory cell is determined by applying two consecutive plate pulses on the ferroelectric capacitor in the memory cell, preamplifying the bit line voltages corresponding to these two plate pulses, and comparing the preamplified voltages. The two consecutive plate pulses have the same polarity.

Abstract: An improved sputtering method for sputter deposition from non-conducting metal oxide, ceramic, and ferroelectric targets is disclosed. Enhancements in deposition rate and composition control have been demonstrated using a pulsed DC sputtering method using a power supply in the frequency range of 100 to 250 KHz and a low frequency RF sputtering method using a power supply in the range of 200 to 500 KHz. The enhancement in composition control comes from an improvement in the sticking efficiencies of the volatile components in ferroelectric films. The low frequency and/or pulsed DC supplies provide lead content control for optimizing ferroelectric performance in pressure regimes that favor better cross wafer composition and thickness uniformity in PVD (Physical Vapor Deposition) sputtering tools.

Abstract: A FRAM configurable output driver circuit allows the user to configure the output driver for either CMOS level push/pull operation or true open drain operation. This configuration is stored in a non-volatile memory including a FRAM cell and a standard logic latch. The configuration data is restored to the latch on powerup. The user is able to change the configuration at any time. Any changes to the configuration are stored in the non-volatile memory.

Abstract: A boosting circuit for a ferroelectric memory using a NAND-INVERT circuit to control one electrode of a ferroelectric boosting capacitor. The other node of the capacitor is connected to the node to be boosted, which may be coupled to a word line. The NAND circuit has two inputs, one being coupled to the word line and another for receiving a timing signal. The timing input rises to initiate the boosting operation, and falls to initiate the removal of the boosted voltage. Only the selected word line in the memory array is affected as any word line remaining at a low logic level “0” will keep the inverter output clamped low. A second embodiment adds a second N-channel transistor in series with the inverter's N-channel transistor to allow for the option of floating the inverter output if it is desired to more quickly drive the word line high during its first upward transition.

Abstract: A method of patterning and etching an integrated circuit ferroelectric capacitor uses a layer of PZT which has the same composition as the capacitor PZT as a temporary encapsulation during PZT grain growth annealing. The temporary encapsulation PZT also serves as a hard mask to pattern the top electrode and the capacitor PZT layers for a capacitor-on-oxide structure, i.e., two-layer-one-step patterning. The process of the present invention can also be modified as a three-layer-one-step patterning process and can be applied to a capacitor-on-plug structure.

Abstract: A transmission line driver circuit that minimizes ringing effects while providing an acceptably fast output response. A plurality of increasingly powerful transistors are activated at different times to drive an output signal without ringing under low impedance conditions and quickly under high impedance conditions. The transmission line driver also includes a digital logic circuit. A strong inverter is connected to a digital logic unit. The strong inverter is activated when the first of two conditions is satisfied: 1) a feedback signal drops below a predetermined level; or 2) an output signal from a final delay is received by the output circuit. In this way, the strong driver will always contribute to driving the output signal, but will only do so when there is little likelihood of ringing.

Abstract: A method for manufacturing a ferroelectric memory cell includes the steps of forming a bottom electrode layer on a substrate, forming a ferroelectric thin film layer on the bottom electrode layer, forming a top electrode on the ferroelectric thin film layer, forming an encapsulating layer on the top electrode, forming a contact hole through the encapsulating layer, and co-annealing the ferroelectric thin film layer and the top electrode after forming the contact hole.

Abstract: An octal transparent latch or D-type register (or flip-flop) integrated circuit device may be packaged in an industry standard logic pin-out and configuration but having nonvolatile properties such as automatically recording the output state in nonvolatile form and restoring it on power up. The nonvolatile memory elements are ideally ferroelectric capacitors, using well known ferroelectric materials such as PZT, SBT, or BST or other ferroelectric materials. EEPROM, Flash, SNOS, or other writeable nonvolatile technologies can also be used. In a particular embodiment disclosed herein, the nonvolatile elements of the integrated circuit device are written only when the latched state changes to reduce write endurance changes thereto and data changes on either the input or output data lines that are not latched have no effect.

Abstract: A ferroelectric capacitor stack for use with an integrated circuit transistor in a ferroelectric memory cell is fabricated by: forming a first dielectric layer over the integrated circuit transistor; forming a bottom electrode over the first dielectric layer, the bottom electrode having a hole located over a first source/drain of the integrated circuit transistor; forming a second dielectric layer over the first dielectric layer and bottom electrode; forming a hole in the second dielectric layer to provide access to the bottom electrode; forming a ferroelectric plug in the hole in the second dielectric layer; forming a top electrode over the second dielectric layer and ferroelectric plug; forming a third dielectric layer over the second dielectric layer and top electrode; forming a first via through the first, second, and third dielectric layers, and through the hole in the bottom electrode, the via having sufficient width to provide access to a lateral edge of the bottom electrode hole; forming a second via

Abstract: A multi-layer ferroelectric thin film includes a nucleation layer, a bulk layer, and an optional cap layer. A thin nucleation layer of a specific composition is implemented on a bottom electrode to optimize ferroelectric crystal orientation and is markedly different from the composition required in the bulk of a ferroelectric film. The bulk film utilizes the established nucleation layer as a foundation for its crystalline growth. A multi-step deposition process is implemented to achieve a desired composition profile. This method also allows for an optional third composition adjustment near the upper surface of the film to ensure compatibility with an upper electrode interface and to compensate for interactions resulting from subsequent processing.

Abstract: A ferroelectric capacitor includes a bottom electrode, a top electrode, and a ferroelectric layer located between the top and bottom electrodes that extends to completely encapsulate the top electrode, except for a contact hole to allow metalization of the top electrode. The total encapsulation of the top electrode reduces the sensitivity of the ferroelectric capacitor to hydrogen and thus improves electrical switching performance.