Abstract: An integrated circuit first-in, first-out ("FIFO") memory device comprises an input bus for receiving data, an input buffer coupled to the input bus for storing the data and at least one dynamic random access memory ("DRAM") array coupled to the input buffer. A write pointer is operative for storing the data in the input buffer to a location within the memory array indicated and an output bus is coupled to the memory array and a read pointer for providing previously written data from the memory array at a location indicated by the read pointer. In a preferred embodiment, the FIFO further comprises at least one static random access memory ("SRAM") cache interposed between the input and output buses and the memory array having a width corresponding to each row of the memory array. In an alternative embodiment, the FIFO memory device includes a "Retransmit" feature which allows data to be read from the device multiple times as well as the Read Pointer to be selectively placed under user control.

Abstract: A preferred state power-up latch circuit includes first and second cross-coupled P-channel transistors coupled to a first source of supply voltage, first and second cross-coupled N-channel transistors coupled to a second source of supply voltage, the transistors being coupled together to form a latch having an output node, in which at least one of the gate lengths is unequal to the other gates lengths in order to establish a preferred state upon power-up, and the gate width of all the transistors is equal.

Abstract: A ferroelectric capacitor includes a bottom electrode, a top electrode, and a ferroelectric layer located between the top and bottom electrodes that extends to completely encapsulate the top electrode, except for a contact hole to allow metalization of the top electrode. The total encapsulation of the top electrode reduces the sensitivity of the ferroelectric capacitor to hydrogen and thus improves electrical switching performance. The encapsulation technique can also be used to improve the performance of ferroelectric transistors and other devices.

Abstract: A memory cell layout for use in a 1T/1C ferroelectric memory array includes an access transistor having a gate coupled to a word line and a current path coupled between a bit line and an internal cell node, a shunt word line extending across the memory cell that is electrically isolated from the word line and the access transistor within the physical boundary of the memory cell, and a ferroelectric capacitor coupled between the internal cell node and a plate line.

Abstract: A test method for characterizing retention performance, both same state and opposite state performance, of ferroelectric capacitors includes the steps of writing an original complementary data state into first and second ferroelectric capacitors after the ferroelectric capacitors have been initialized into an initial valid data state. The first and second ferroelectric capacitors are then subjected to time and temperature stress. The original complementary data state from the first and second ferroelectric capacitors is then read, and same state charge (Q.sub.SS) information is collected. An opposite complementary data state is then written in the first and second capacitors. After a short time interval, possibly at an elevated temperature, the opposite complementary data state from the first and second ferroelectric capacitors is read to gather opposite state charge (Q.sub.OS) information. The original complementary data state is then written into the first and second ferroelectric capacitors.

Abstract: A method of driving a sense amplifier having at least one input/output node and at least one latch node the method includes the steps of initially setting the latch node to a first logic state such that the sense amplifier is disabled, adjusting the latch node voltage in one or more discrete levels, and finally setting the latch node to a second logic state such that the sense amplifier is enabled.

Abstract: A bootstrap circuit suitable for use in driving the word line of a FRAM.RTM. memory circuit is energized by a VDD power supply voltage. The bootstrap circuit includes a first N-channel MOS transistor wherein the source/drain forms the input of the circuit. A second N-channel MOS transistor is included wherein one of the source/drains receives a clock signal, and the other source/drain forms the output, which drives the word line. The gate of the second transistor is coupled to the other source/drain of the first transistor. The bootstrap circuit includes further circuitry for generating a voltage greater tan the VDD power supply voltage that is coupled to the gate of the first transistor. A capacitor or capacitor-connected transistor is coupled between the input and the gate of the first transistor, and a third transistor has one source/drain coupled to the gate of the first transistor, and the other source/drain receives a control signal, and the gate is coupled to the VDD power supply.

Abstract: A plate line segmentation scheme for a 1T/1C ferroelectric memory architecture includes an array of 1T/1C ferroelectric memory cells, word lines corresponding to each row of 1T/1C ferroelectric memory cells, and plate lines corresponding to each row of 1T/1C ferroelectric memory cells, wherein each plate line is divided into two or more equal plate line segments, only one of which is driven when a corresponding word line is selected.

Abstract: A yield enhancement technique for integrated circuit processing which reduces the deleterious effects of H.sub.2 O contamination which is absorbed by conventional dielectric films resulting in an undesired subsequent out-diffusion of hydrogen when the integrated circuit die is subsequently subjected to relatively high processing temperatures such as those experienced in CERDIP packaging. The technique disclosed comprises the formation of an interlevel dielectric layer having hydrophilic properties (for example, 7.5% phosphorus doped TEOS) at least partially surrounding a device on the integrated circuit which layer is then subjected to an annealing operation to drive off at least a portion of any moisture present therein.

Abstract: A reference cell layout for use in a 1T/1C ferroelectric memory array includes a transistor of a first polarity type having a gate coupled to a reference word line and a current path coupled between a bit line and an internal cell node, a transistor of a second polarity type having a gate coupled to a pre-charge line and a current path coupled between a source of power supply voltage and the internal cell node, a shunt reference word line extending across the reference cell that is electrically isolated from the reference word line, the pre-charge line and the transistors within the physical boundary of the memory cell, and a ferroelectric capacitor coupled between the internal cell node and a reference plate line.

Abstract: An iridium oxide local interconnect method for a ferroelectric memory cell includes the steps of forming a conductive layer that extends from a source/drain contact of the transistor proximate to an electrode contact of the ferroelectric capacitor and forming an iridium oxide local interconnect extending from the source/drain contact of the transistor to the electrode contact of the ferroelectric capacitor. The conductive layer is laterally terminated not less than one-half micron from the electrode contact of the ferroelectric capacitor. The conductive layer can include an upper iridium layer and a bottom titanium nitride layer, or can include a single layer of completely reacted titanium nitride. After the local interconnect is formed a top oxide layer is deposited. A late recovery anneal is then performed in oxygen at an elevated temperature to rejuvenate the electrical characteristics of the ferroelectric capacitor. Finally, a bit line contact is opened and metalized.

Abstract: The method and apparatus of the current invention relates to an intelligent cache management system for servicing a main memory and a cache. The cache resources are allocated to segments of main memory rows based on a simple or complex allocation process. The complex allocation performs a predictive function allocating scarce resources based on the probability of future use. The apparatus comprises a main memory coupled by a steering unit to a cache. The steering unit controls where in cache a given main memory row segment will be placed. The operation of the steering unit is controlled by an intelligent cache allocation unit. The unit allocates new memory access requests cache locations which are least frequently utilized. Since a given row segment may be placed anywhere in a cache row, the allocation unit performs the additional function of adjusting the column portion of a memory access request to compensate for the placement of the requested segment in the cache.

Abstract: A method of driving a selected plate line segment in a 1T/1C memory, the method including the steps of logically combining an odd word line signal and an even word line signal to form a first logic signal, logically combining the first logic signal with a plate clock signal to form a second logic signal, latching the second logic signal, and driving the selected plate line segment with the latched second logic signal.

Abstract: A sense amplifier cell layout for use in a 1T/1C ferroelectric memory array includes a first sense amplifier having two input/output nodes for receiving a first bit line signal and a first inverted bit line signal and a second sense amplifier having two input/output nodes for receiving a second bit line signal and a second inverted bit line signal, wherein the combined width of the first and second sense amplifiers is substantially the same as the width of two columns of 1T/1C memory cells used in the array.

Abstract: A lead zirconate titanate ferroelectric film used as the dielectric layer in a ferroelectric capacitor is doped with calcium and/or strontium, and the lead composition selected to improve data retention performance. The chemical formula for the ferroelectric film is: (Pb.sub.v Ca.sub.w Sr.sub.x La.sub.y)(Zr.sub.z Ti.sub.(1-z))O.sub.3 ; wherein v is ideally between 0.9 and 1.3; w is ideally between 0 and 0.1; x is ideally between 0 and 0.1; y is ideally between 0 and 0.1, and z is ideally between 0 and 0.9. In addition, the chemical composition of the ferroelectric film is further specified in that the measured opposite state charge at a specific time and temperature of the ferroelectric capacitor is greater than eight micro-Coulombs per square centimeter, and the rate of imprint degradation is less than fifteen percent per decade.

Abstract: A reference cell for a 1T/1C ferroelectric memory includes a transistor of a first polarity type having a gate coupled to a reference cell word line, and a current path coupled between a bit line and an internal reference cell node, a transistor of a second polarity type having a gate coupled to a pre-charge line, and a current path coupled between a source of supply voltage and the internal reference cell node, and a ferroelectric capacitor coupled between the internal reference cell node and ground.

Abstract: A single integrated circuit for an RF/ID transponder includes a nonvolatile memory portion, which is ideally a ferroelectric memory, digital logic, digital interface circuitry, and differential analog driver circuitry for driving an antenna that is contained within the RF/ID transponder, but external to the integrated circuit. In series with each leg of the differential analog driver circuitry, and also fabricated on the single integrated circuit, are two groups of serially connected resistors. All circuit nodes associated with the resistors are connected to a signal level control logic block that is in communication with the on-chip digital logic block. The signal level control logic block is used to selectively control the output resistance of the driver circuitry such that a proper balance between incoming and outgoing signal levels is achieved.

Abstract: A ferroelectric capacitor includes a bottom electrode, a top electrode, and a ferroelectric layer located between the top and bottom electrodes that extends to completely encapsulate the top electrode, except for a contact hole to allow metalization of the top electrode. The total encapsulation of the top electrode reduces the sensitivity of the ferroelectric capacitor to hydrogen and thus improves electrical switching performance.

Abstract: An architecture for a serial ferroelectric memory device that incorporates the provision of a latch intermediate the device memory array and column decoder of a width equal to a row in the array. In operation, the presence of the latch ensures that each write access to the memory device loads a row into the latch. Data is then modified while retained in the latch and written back to the memory array at the end of the cycle. A read operation can perform a write-back from the latch to the memory array at the beginning of the cycle after data is loaded into the latch. The addition of the latch intermediate the column decoder and the memory array then serves to ensure that for typical block read operations each column of the memory array will experience the same single write back cycle. As a consequence, data retention reliability for the memory device is improved by mitigating the effects of disparate imprint on the memory cells of the memory array.

Abstract: A semiconductor memory device, divided into plural blocks, comprising: a memory array having a non-volatile memory element which makes the read cycle and the write cycle to be substantially equivalent; plural storage elements storing the information of write protection/permission corresponding to each said block respectively; and a setting circuit to set the information of write protection/permission to said plural storage elements, wherein said setting circuit sets the write-protection information to said plural storage elements at the write cycle after designated plural read cycles. Therefore, the write protection/permission can be set by the unit of block, block by block, so that the write-protected ROM and the RAM can be set freely. Furthermore, the complexity of the setting procedure of write protection/permission may prevent the accidental false setting caused by a system runaway and so forth.