Abstract: An integrated circuit capacitor and method for making the same utilizes a ferroelectric dielectric, such as lead-zirconate-titanate ("PZT"), to produce a high value peripheral capacitor for integration on a common substrate with a ferroelectric memory array also utilizing ferroelectric memory cell capacitors as non-volatile storage elements. The peripheral capacitor is linearly operated in a single direction and may be readily integrated to provide capacitance values on the order of 1-10 nF or more utilizing the same processing steps as are utilized to produce the alternately polarizable memory cell capacitors. The high value peripheral capacitor has application, for example, as a filter capacitor associated with the on-board power supply of a passive radio frequency ("RF") identification ("ID") transponder.

Abstract: A dual-level metalization method for ferroelectric integrated circuits includes the steps forming a planarized oxide layer over a partially formed integrated circuit ferroelectric device, forming a cap layer over the planarized oxide layer, forming vias into the planarized oxide layer and cap layer to provide access to the desired first-level metal contacts, and metalizing the selected first-level metal contacts with second-level metal. The cap layer can be doped or undoped titanates, zirconates, niobates, tantalates, stanates, hafnates, or manganates such as doped and undoped PZT (lead zirconate titanate), BST (barium strontium titanate), or SBT (strontium bismuth tantalate).

Abstract: An integrated circuit first-in, first-out ("FIFO") memory device comprises an input bus for receiving data, an input buffer coupled to the input bus for storing the data and at least one dynamic random access memory ("DRAM") array coupled to the input buffer. A write pointer is operative for storing the data in the input buffer to a location within the memory array indicated and an output bus is coupled to the memory array and a read pointer for providing previously written data from the memory array at a location indicated by the read pointer. In a preferred embodiment, the FIFO further comprises at least one static random access memory ("SRAM") cache interposed between the input and output buses and the memory array having a width corresponding to each row of the memory array.

Abstract: A cross-coupled sense amplifier includes a voltage-compensating balancing resistor serially connected between the drain of one of the P-channel transistors in the sense amplifier and the corresponding sensing/bit line node. The value of the balancing resistor is optimized so that the voltage imbalance between the P-channel transistor is minimized and sense amplifier sensitivity is maximized. A balancing resistor can also be placed in the N-channel transistors in the sense amplifier if desired. The balancing resistor in a typical application is about 100 to 200 ohms and fabricated from polysilicon.

Abstract: A column decoder cell layout for use in a 1T/1C ferroelectric memory array includes a first column decoder section having two input nodes for receiving a first input/output signal and a first inverted input/output signal, two output nodes for providing a first bit line signal and a first inverted bit line signal, and a column decode node for receiving a column decode signal, a second column decoder section having two input nodes for receiving a second input/output signal and a second inverted input/output signal, two output nodes for providing a second bit line signal and a second inverted bit line signal, and a column decode node for receiving the column decode signal, wherein the width of the column decoder cell is substantially the same as the width of two columns of 1T/1C memory cells used in the array.

Abstract: A data processor incorporating a memory array which is selectably configurable as either read/write or read only memory or the combination of both read/write and read only memory includes a memory mapper for receiving logical addresses from an arithmetic logic unit ("ALU") and converting the same to physical addresses within the memory array in accordance with configuration instructions stored in a local non-volatile memory. By utilizing a common memory technology for the memory array, such as non-volatile ferroelectric random access memory ("FRAM"), the proportions and layout of the memory array which may be utilized for MPU instructions and data may be selectably controlled. The use of a memory mapper also allows for the establishment of an effective password or encryption protection function for the memory array data of particular utility in conjunction with radio frequency identification ("RF/ID") transponders and other applications which must store sensitive data in non-volatile storage.

Abstract: A charge pump for increasing the value of an input voltage includes a plurality of serially coupled charge pump stages, wherein each charge pump stage includes a P-channel pass transistor coupled to a first end of a capacitor. The gates of the P-channel pass transistors and the second ends of the capacitors in odd-numbered charge pump stages receive a first phase clock signal, and the gates of the pass transistors and the second ends of the capacitors in even-numbered charge pump stages receive a second phase clock signal, except that the second end of the capacitor in the last charge pump stage is coupled to ground. To increase the value of the capacitors in an integrated circuit embodiment all of the capacitors, except for the capacitor in the last stage, are ideally ferroelectric capacitors. In a preferred embodiment, the charge pump is one component in a regulated charge pump system that also includes a voltage regulator and a controlled oscillator.

Abstract: A method of operating a 1T/1C ferroelectric memory having a memory cell coupled to a word line, a bit line, and a plate line, includes the steps of turning on the word line, energizing the plate line to establish a charge on the bit line, turning off the word line, and sensing the charge on the bit line while the word line is off.

Abstract: A power-on detect circuit includes: a resistor divider having a first node, a second node coupled to ground, and a center tap; a bandgap circuit for providing a reference voltage; a differential amplifier having a first input for receiving the reference voltage, a second input coupled to the center tap of the bandgap reference voltage circuit, and an output for providing a power-on detect signal; and a suppression circuit for coupling the first node of the resistor divider to a source of supply voltage once the reference voltage substantially achieves a stable reference voltage level. The suppression circuit has an input for receiving a trigger voltage generated in the bandgap circuit, and an output coupled to the first node of the resistor divider.

Abstract: A ferroelectric capacitor includes a bottom electrode, a top electrode, and a ferroelectric layer located between the top and bottom electrodes that extends to completely encapsulate the top electrode, except for a contact hole to allow metalization of the top electrode. The total encapsulation of the top electrode reduces the sensitivity of the ferroelectric capacitor to hydrogen and thus improves electrical switching performance.

Abstract: A memory suitable for integration having a memory structure where at least one capacitor formed by using a ferroelectric is integrated on a semiconductor device substrate. In a unit cell structure forming the memory, an upper electrode, located at an upper position among electrodes constituting the capacitor, is directly connected to a high density diffusion layer constituting a MOS transistor.

Abstract: A voltage boost circuit allows a reference input voltage to be boosted in a manner that is less sensitive to variations in power supply voltage levels, temperature, and semiconductor process used. A nominal boost voltage of approximately 1.5 volts is supplied, even at very low power supply voltages. A boost voltage less than 1.5 volts is supplied down to power supply voltages of approximately 1.8 volts.

Abstract: A power-on detect circuit includes: a resistor divider having a first node, a second node coupled to ground, and a center tap; a bandgap circuit for providing a reference voltage; a differential amplifier having a first input for receiving the reference voltage, a second input coupled to the center tap of the bandgap reference voltage circuit, and an output for providing a power-on detect signal; and a suppression circuit for coupling the first node of the resistor divider to a source of supply voltage once the reference voltage substantially achieves a stable reference voltage level. The suppression circuit has an input for receiving a trigger voltage generated in the bandgap circuit, and an output coupled to the first node of the resistor divider.

Abstract: An iridium oxide local interconnect method for a ferroelectric memory cell includes the steps of forming a conductive layer that extends from a source/drain contact of the transistor proximate to an electrode contact of the ferroelectric capacitor and forming an iridium oxide local interconnect extending from the source/drain contact of the transistor to the electrode contact of the ferroelectric capacitor. The conductive layer is laterally terminated not less than one-half micron from the electrode contact of the ferroelectric capacitor. The conductive layer can include an upper iridium layer and a bottom titanium nitride layer, or can include a single layer of completely reacted titanium nitride. After the local interconnect is formed a top oxide layer is deposited. A late recovery anneal is then performed in oxygen at an elevated temperature to rejuvenate the electrical characteristics of the ferroelectric capacitor. Finally, a bit line contact is opened and metalized.

Abstract: A reference cell for a 1T-1C memory is disclosed for use in either an open or folded memory cell array. Each reference cell has two outputs each coupled to a bit line that each develop a voltage substantially half of that developed by a ferroelectric memory cell. The reference voltages and memory cell voltage are than resolved by a sense amplifier. Each reference cell includes two ferroelectric capacitors that are the same size and fabricated with the identical process as the memory cell ferroelectric capacitors. Any changes in the memory cell capacitor similarly affects the reference cell capacitor, and thus the reference voltage is always substantially half of that developed by the memory cell. The reference cells include a number of timing inputs, which control charge sharing and configure the cell to operate in either a DRAM or FRAM.RTM. mode. In a first embodiment, one of the reference cell capacitors is poled.

Abstract: A semiconductor memory device, divided into plural blocks, includes a memory array having a non-volatile memory element in which address access times for the read cycle and the write cycle are substantially equivalent to one another (for example, a ferroelectric memory element). Plural storage elements stores the information for write protection/permission corresponding to each of the blocks, respectively. A setting circuit is provided to set the information for write protection/permission to the plural storage elements. The setting circuit sets the write-protection information to the plural storage elements at the write cycle after designated plural read cycles. Therefore, the write protection/permission can be set in block units block by block, so that the write-protected areas for a ROM and a RAM formed by the non-volatile memory element can be set freely.

Abstract: A circuit and method for reducing compensation of a ferroelectric capacitor in a cell of a memory array allows the capacitor's hysteresis loop to be repositioned toward its uncompensated position by pulsing the electrodes of the memory cell capacitors, via the memory array plate line, one or more additional times whenever a "write" occurs to the memory array. As a result, the ferroelectric capacitor delivers a signal of greater strength to the memory device sense amps upon a subsequent "read" operation significantly enhancing overall reliability and yield yet without reducing overall device endurance.

Abstract: A test mode circuit for an integrated circuit includes a high voltage detector having an input for receiving a high voltage signal, a Schmitt trigger having an input coupled to the output of the high voltage detector, a latch having an input coupled to the output of the Schmitt trigger and an output for providing a test mode signal in a test operational mode, and additional control circuitry for disabling the high voltage detector and Schmitt trigger so that substantially all of the active current flow in the high voltage detector and Schmitt trigger is eliminated in a normal operational mode. The test mode circuit further includes circuitry for preventing a reset condition in the latch during the test mode until a power-down condition occurs. A glitch filter is also included, which is interposed between the output of the Schmitt trigger and the input to the latch.

Abstract: A lead zirconate titanate ferroelectric film used as the dielectric layer in a ferroelectric capacitor is doped with calcium and/or strontium, and the lead composition selected to improve data retention performance. The chemical formula for the ferroelectric film is: (Pb.sub.v Ca.sub.w Sr.sub.x La.sub.y)(Zr.sub.z Ti.sub.(1-z))O.sub.3 ; wherein v is ideally between 0.9 and 1.3; w is ideally between 0 and 0.1; x is ideally between 0 and 0.1; y is ideally between 0 and 0.1, and z is ideally between 0 and 0.9. In addition, the chemical composition of the ferroelectric film is further specified in that the measured opposite state charge at a specific time and temperature of the ferroelectric capacitor is greater than eight micro-Coulombs per square centimeter, and the rate of imprint degradation is less than fifteen percent per decade.

Abstract: A system and method for selective write protection for a non-volatile memory device which comprises a superset of the existing JEDEC 21-C standard and in which user definable portions of a non-volatile memory device can be write protected instead of only the entire device. The write-protection technique of the present invention can be selectably enabled or disabled dynamically as determined by a user. Moreover, the system and method of the present invention provides for storage of the device write-protection configuration in non-volatile memory in order that the device can be restored to its last known write-protection state in the event it is powered down or the current configuration is otherwise lost.