Abstract: A method of fabricating a metal-ferroelectric-metal ("MFM") capacitor includes the steps of depositing a silicon dioxide layer on a silicon or other substrate, a lower platinum or other noble metal electrode, a PZT or other ferroelectric material dielectric layer, and an upper platinum or other noble metal electrode. The upper electrode and ferroelectric dielectric layer are patterned and etched according to a first pattern corresponding to the final dimensions of the ferroelectric dielectric layer. The upper electrode and lower electrode are subsequently patterned and etched according to a second pattern corresponding to the final dimensions of one or more upper electrodes and the final extent of the lower electrode. The second etching step leaves a benign vestigial upper electrode feature. An oxide layer is finally deposited over the entire surface of the MFM capacitor structure, which is etched and metalized over desired upper and lower electrode contacts.

Abstract: A ferroelectric memory array includes a word line coupled to a row of ferroelectric memory cells and a word line driver circuit for establishing a full power supply voltage on the word line. A bootstrapping circuit is coupled between the word line and a boost line for receiving a boost signal. The bootstrapping circuit includes a ferroelectric capacitor and coupling circuitry for coupling the ferroelectric capacitor between the boost line and the word line in a first operational mode such that the peak voltage on the word line is greater than the power supply voltage, and for isolating the ferroelectric capacitor from the boost line in a second operational mode.

Abstract: A system and method for mitigating undesired imprint effects in a ferroelectric memory array through the addition of a complementary data path which allows user data to be written to the array in an inverted state and then subsequently read out from the array in a re-inverted state in response to the state of at least one indicator bit corresponding to each row of the array.

Abstract: An enhanced DRAM contains embedded row registers in the form of latches. The row registers are adjacent to the DRAM array, and when the DRAM comprises a group of subarrays, the row registers are located between DRAM subarrays. When used as on-chip cache, these registers hold frequently accessed data. This data corresponds to data stored in the DRAM at a particular address. When an address is supplied to the DRAM, it is compared to the address of the data stored in the cache. If the addresses are the same, then the cache data is read at SRAM speeds. The DRAM is decoupled from this read. The DRAM also remains idle during this cache read unless the system opts to precharge or refresh the DRAM. Refresh or precharge occur concurrently with the cache read. If the addresses are not the same, then the DRAM is accessed and the embedded register is reloaded with the data at that new DRAM address.

Abstract: An enhanced dynamic random access memory (DRAM) contains embedded row registers in the form of latches. The row registers are adjacent to the DRAM array, and when the DRAM comprises a group of subarrays, the row registers are located between DRAM subarrays. When used as on-chip cache, these registers hold frequently accessed data. This data corresponds to data stored in the DRAM at a particular address. When an address is supplied to the DRAM, it is compared to the address of the data stored in the cache. If the addresses are the same, then the cache data is read at static random access memory (SRAM) speeds. The DRAM is decoupled from this read. The DRAM also remains idle during this cache read unless the system opts to precharge or refresh the DRAM. Refresh or precharge occur concurrently with the cache read. If the addresses are not the same, then the DRAM is accessed and the embedded register is reloaded with the data at that new DRAM address.

Abstract: A test method for ferroelectric memories includes the steps of: functionally testing the ferroelectric memories to determine functional yield; storing the ferroelectric memories for at least eight hours; writing an initial pattern into the ferroelectric memories; baking the ferroelectric memories; reading the initial pattern to determine same state yield; writing an inverse pattern into the ferroelectric memories; reading the inverse pattern to determine opposite state yield; and again writing the initial pattern into the ferroelectric memories. The steps of baking, reading the initial pattern and writing the inverse pattern, and reading the inverse pattern and writing the initial pattern are repeated for a number of test cycles. The ferroelectric memories are baked at a temperature of about 150.degree. C. for a predetermined duration that is incremented with each successive test cycle.

Abstract: In fabricating a source/drain electrode of an integrated circuit transistor and a contact window for it: (1) establishing a structure with a window over the source/drain region next to a gate electrode and isolation structure; (2) establishing a dielectric layer covering the isolation structure, the window, and gate electrode; (3) implanting a moderate concentration of impurities into the source/drain region through said dielectric layer so that the moderate concentration region extends partially under the gate electrode; (4) removing the horizontal portions of the dielectric layer with an anisotropic etch thereby leaving the dielectric on vertical side walls; (5) establishing a region of titanium silicide over the moderately dosed source/drain region and establishing a titanium nitride layer over the isolation structure, windows, and gate electrode; (6) establishing a layer of silicon nitride over the titanium nitride layer; (7) implanting the substrate with a relatively heavier dose of ions through the sili

Abstract: An integrated circuit capacitor and method for making the same utilizes a ferroelectric dielectric, such as lead-zirconate-titanate ("PZT"), to produce a high value peripheral capacitor for integration on a common substrate with a ferroelectric memory array also utilizing ferroelectric memory cell capacitors as non-volatile storage elements. The peripheral capacitor is linearly operated in a single direction and may be readily integrated to provide capacitance values on the order of 1-10 nF or more utilizing the same processing steps as are utilized to produce the alternately polarizable memory cell capacitors. The high value peripheral capacitor has application, for example, as a filter capacitor associated with the on-board power supply of a passive radio frequency ("RF") identification ("ID") transponder.

Abstract: A ferroelectric nonvolatile random access memory array includes multiple ferroelectric memory cells arranged in rows and columns, a word line coupled to a word line input of each of the ferroelectric memory cells in a row, and a bit line coupled to a bit line input of each of the ferroelectric memory cells in a column. The array also includes multiple plate lines, each plate line being arranged into a plurality of plate line segments each coupled to a plate line input of a predetermined number of the ferroelectric memory cells in a row, and multiple NMOS plate line segment drivers coupled to each of the plate line segments for selectively driving the corresponding plate line segment to a full rail voltage. The rows of ferroelectric memory cells and the NMOS plate line segment drivers have substantially the same layout pitch. The plate line segment drivers are each coupled to a center portion of the corresponding plate line segment.

Abstract: A circuit and method for reducing compensation of a ferroelectric capacitor in a cell of a memory array allows the capacitor's hysteresis loop to be repositioned toward its uncompensated position by pulsing the electrodes of the memory cell capacitors, via the memory array plate line, one or more additional times whenever a "write" occurs to the memory array. As a result, the ferroelectric capacitor delivers a signal of greater strength to the memory device sense amps upon a subsequent "read" operation significantly enhancing overall reliability and yield yet without reducing overall device endurance.

Abstract: A ferroelectric memory cell has an FET covered by an insulation layer and a ferroelectric capacitor located thereover. An interconnect couples an upper plate of the ferroelectric capacitor to a source/drain of the transistor. In a method of forming the cells, after the transistor is fabricated, the bottom electrode and ferroelectric dielectric are established, but the top capacitor electrode is not added until a further layer of insulation is added over the ferroelectric and windows are opened in it. One window is for the top electrode and another window is to one source/drain region of the FET.

Abstract: A method for passivating an integrated circuit includes the RF sputtering of a hard passivation layer on the surface of the integrated circuit. The hard passivation layer can be a ceramic material such as various doped and undoped titanates, zirconates, niobates, tantalates, stanates, hafnates, and manganates, in either their ferroelectric or non-ferroelectric phases. Other exotic, hard, and usually non-ferroelectric materials not normally found in integrated circuit processing such as carbides may also be used. If the integrated circuit sought to be passivated contains ferroelectric devices, the hard passivation layer can be fabricated out of the same material used in the integrated ferroelectric devices. An optional silicon dioxide insulating layer can be deposited on the surface of the integrated circuit before the hard passivation layer is deposited. The optional silicon dioxide layer is used to prevent any possible contamination of the integrated circuit by the passivation layer.

Abstract: A reference cell for a IT-1C memory can be used in either an open or folded memory cell array. Each reference cell has two outputs each coupled to a bit line that each develop a voltage substantially half of that developed by a ferroelectric memory cell. The reference voltages and memory cell voltage are than resolved by a sense amplifier. Each reference cell includes two ferroelectric capacitors that are the same size and fabricated with the identical process as the memory cell ferroelectric capacitors. Any changes in the memory cell capacitor similarly affects the reference cell capacitor, and thus the reference voltage is always substantially half of that developed by the memory cell. The reference cells include a number of timing inputs, which control charge sharing and configure the cell to operate in either a DRAM or FRAM.RTM. mode. In a first embodiment, one of the reference cell capacitors is poled.

Abstract: A single address register control technique for a memory controller allows both cache "reads" and page-mode "writes" to be implemented without requiring separate hardware address registers for each function. Because both functions may be implemented with virtually no performance loss in a high performance memory system using a single address register, a comparator, and one additional register, the costs and other disadvantages inherent in otherwise replicating control registers are obviated.

Abstract: A method of operating a nonvolatile ferroelectric memory cell including a polarized ferroelectric capacitor includes the steps of reading and restoring a first polarization state of the ferroelectric capacitor at a voltage not sufficient to fully saturate the ferroelectric capacitor, but sufficient to release a detectable amount of charge corresponding to the first polarization state. Writing a second polarization state in the ferroelectric capacitor is performed at a voltage sufficient to fully saturate the ferroelectric capacitor. During a read and restore operation, the plate line of the memory cell is pulsed with first and second voltage pulses that each have a voltage magnitude less than the normal five volt logic pulse, for example four volts. During a write operation, the plate line of the memory cell is pulsed with a voltage that has a magnitude greater than the normal five volt logic pulse, for example six to seven volts.

Abstract: In a ferroelectric memory cell having a plate line, a word line and a bit line coupled to a sense amplifier, a sensing method includes the steps of precharging the bit line to a logic one voltage, setting the word and plate lines to an initial logic zero voltage, stepping the word line from the initial logic zero voltage to the logic one voltage, stepping the plate line from the initial logic zero voltage to the logic one voltage, activating the sense amplifier to resolve voltage developed on the bit line to a full logic voltage while the word and plate lines are at the logic one voltage, and returning the word and plate lines to the initial logic zero voltage.

Abstract: Ferroelectric capacitors in an integrated memory are renewed to improve retention performance. The renewal method is performed on a wafer containing ferroelectric memory die. In one method, a rejuvenation anneal is performed after all electrical tests, including those at elevated temperatures, have been accomplished, but before the failed die have been inked. The rejuvenation anneal is performed at or above the Curie temperature of the ferroelectric material. In the preferred embodiment, the ferroelectric material is PZT, and the rejuvenation anneal is a thermal treatment at 400.degree. Centigrade in a nitrogen flow of roughly ten liters per minute for about an hour. In another method, separate electrical cycling and depoling operations are performed to provide the equivalent benefits of the single rejuvenation anneal. The electrical cycling operation is accomplished by writing about one hundred cycles at five volts alternating logic states into each ferroelectric capacitor into the array.

Abstract: A semiconductor device having a ferroelectric film or a polycrystalline silicon gate, a humidity-resistant hydrogen barrier film, like TiN film, TiON film, etc., formed by hydrogen non-emission film forming method over the ferroelectric film or the polycrystalline silicon gate.

Abstract: A semiconductor manufacturing method is directed to forming a ferroelectric film, and in particular a ferroelectric film of the bismuth layer structure type, that has a significant component of reversible polarization perpendicular to the plane of the electrodes. The manufacturing method is conducted at low temperatures on commercially suitable electrodes and is compatible with conventional CMOS fabrication techniques. A ferroelectric strontium-bismuth-tantalate ("SBT") film is formed using two sputtering targets. A first sputtering target is comprised primarily of bismuth oxide (Bi.sub.2 O.sub.3) and a second sputtering target is comprised primarily of SBT. An initial layer of bismuth oxide is formed on the bottom electrode of a ferroelectric capacitor stack. The initial layer of bismuth oxide is directly followed by a sputtered layer of SBT.

Abstract: A method of forming a local interconnect for a ferroelectric memory cell includes the steps of simultaneously opening top electrode and source/drain contacts to the ferroelectric memory cell, sputtering a first blanket metal layer comprised of platinum or palladium on a top surface of the ferroelectric memory cell, annealing the ferroelectric memory cell to simultaneously recover damage in a ferroelectric capacitor dielectric of the memory cell, and to silicidize the first metal layer in the source/drain contact, sputtering a second blanket metal layer comprised of titanium nitride on a top surface of the first metal layer, and selectively etching the first and second metal layers to form the local interconnect between the top electrode and source/drain contacts of the ferroelectric memory cell.