Abstract: The present invention discloses a DAC method having signal calibration mechanism used in a DAC circuit having thermometer-controlled current sources generating an output analog signal according to a total current thereof and a control circuit. Current offset values of the current sources are retrieved. The current offset values are sorted to generate a turn-on order, in which the current offset values are separated into current offset groups according to the turn-on order, the signs of each neighboring two groups being opposite such that the current offset values cancel each other when the current sources turn on according to the turn-on order to keep an absolute value of a total offset not larger than a half of a largest absolute value of the current offset values. The current sources are turned on based on the turn-on order according to a thermal code included in an input digital signal.

Abstract: A bootstrapped switch includes a sampling transistor, a bootstrapped circuit, and a buffer circuit. The sampling transistor is configured to be selectively turned on according to a level of a control node, in order to transmit an input signal from a first terminal of the sampling transistor to a second terminal of the sampling transistor, in which a body of the sampling transistor is configured to receive a buffer signal. The bootstrapped circuit is configured to pull up the level of the control node, such that a constant voltage difference is present between the control node and the first terminal of the sampling transistor during a turn-on interval of the sampling transistor. The buffer circuit is configured to generate the buffer signal according to the input signal.

Abstract: An audio processing device includes: a sound level measuring circuit arranged to operably generate multiple sound level values, wherein the multiple sound level values respectively correspond to the sound levels generated by an audio playback device at multiple time points or the sound levels received by a microphone at multiple time points; an audio dose calculating circuit coupled with the sound level measuring circuit and arranged to operably generate an audio dose value corresponding to a measuring period based on the multiple sound level values and contents of a weighting table; a control circuit coupled with the audio dose calculating circuit and arranged to operably compare the audio dose value with a dose threshold to determine whether to generate a control signal or not; and an indication signal generating circuit coupled with the control circuit and arranged to operably generate a corresponding indication signal according to the control signal.

Abstract: A chip includes a first circuit under test, a second circuit under test, and a clock masking circuit. The first circuit under test is coupled to the second circuit under test. The clock masking circuit includes a first clock control circuit, a second clock control circuit, and an enabling circuit. The first clock control circuit is configured to provide a first clock signal for the first circuit under test according to a first enable signal and an initial clock signal. The second clock control circuit is configured to provide a second clock signal for the second circuit under test according to a second enable signal and the initial clock signal. The enabling circuit is configured to provide a first enable signal for the first clock control circuit and a second enable signal for the second clock control circuit.

Abstract: A resistive attenuator and a method for improving linearity of the resistive attenuator are provided. The resistive attenuator includes a first transistor, an attenuation circuit and a compensation circuit, wherein both the first transistor and the attenuation circuit are coupled between an input terminal and an output terminal of the resistive attenuator, and the compensation circuit is coupled to the first transistor. The first transistor is configured to provide a first signal path between the input terminal and the output terminal. The attenuation circuit is configured to provide a second signal path between the input terminal and the output terminal, wherein signal attenuation of the second signal path is greater than signal attenuation of the first signal path. The compensation circuit is configured to compensate nonlinear distortion caused by the first transistor.

Abstract: A circuit for preventing current backflow includes: a signal connection terminal, a power input terminal, an internal power supply terminal, an electrostatic protection circuit, a first switch element and a cut-off control circuit. The electrostatic protection circuit is coupled to the signal connection terminal and the internal power supply terminal. The first switch element is coupled between the power input terminal and the internal power supply terminal. The cut-off control circuit is coupled to the signal connection terminal, the power input terminal and the first switch element. The cut-off control circuit controls the switching of the first switch element according to a voltage of the signal connection terminal and a voltage of the power input terminal.

Abstract: A super resolution image generating device capable of processing an image flexibly includes a scaling-up circuit, a front-end circuit, a first branch circuit, a second branch circuit, and an arithmetic circuit. The scaling-up circuit scales up the image to generate an enlarged image including N pixel values. The front-end circuit extracts features of the image to generate a front-end feature map. The first branch circuit extracts features of the front-end feature map to generate a first feature map, and scales up the first feature map to generate N first values. The second branch circuit processes the front-end feature map to generate a second feature map, scales up the second feature map to generate N second values, and processes the N second values to generate N processed values. The arithmetic circuit combines the N pixel values, the N first values, and the N processed values to generate a super resolution image.

Abstract: An electronic system test method, comprising: (a) inputting a victim test pattern to a victim signal path of a target electronic system and simultaneously inputting at least one aggressor test pattern to at least one aggressor signal path of the target electronic system, according to a major set of test patterns comprising a plurality of minor set of test patterns; (b) acquiring a output response corresponding to the step (a); and (c) after changing the victim test pattern or the aggressor test pattern, and after repeating the step (a) and the step (b) until all of the major test patterns set are used thereby acquiring a plurality of the output responses, determining a combination level according to the output responses. The victim test pattern is an X bit pattern and the aggressor test pattern is a Y bit pattern, X and Y are positive integers larger than or equal to 3.

Abstract: A Bluetooth communication system includes: a Bluetooth host device; and a Bluetooth device set which including a first member device and a second member device. The first member device transmits a device information of the first member device to the Bluetooth host device. The Bluetooth host device controls a display device to display a candidate device list, and to display a single device item in the candidate device list to represent the Bluetooth device set, but does not simultaneously display two device items in the candidate device list to represent the first member device and the second member device. The Bluetooth host device further establishes a connection with the first member device to conduct pairing procedure to generate a first cypher key after receiving a selection command. The first member device further establishes a connection with the Bluetooth host device to conduct pairing procedure to generate a second cypher key.

Abstract: A dongle coupled between a power supplying device for supplying power and a power receiving device for receiving power includes a downstream facing port (DFP), an upstream facing port (UFP) and a controller. The controller is arranged to control deliveries of the power and messages between the power supplying device and the power receiving device. In response to a first power request message received from the power receiving device, the controller is arranged to determine whether a power type request by the power receiving device is Programmable Power Supply (PPS) according to the first power request message. When determining that the power type request by the power receiving device is PPS, the controller is arranged to start first waiting timer, and when the first waiting timer expires, the controller is arranged to send a request accept message to the power receiving device through the UFP.

Abstract: An image display system includes a display device, a second memory circuit, and an image processor circuit. The display device includes a panel and a first memory circuit, in which the first memory circuit is configured to store first predetermined data for controlling the panel. The second memory circuit is configured to store second predetermined data. The image processor circuit is configured to read first part data in the first predetermined data and second part data in the second predetermined data and compare the first part data with the second part data. If the first part data is identical to the second part data, the image processor circuit is further configured to output a driving signal according to the second predetermined data to control the panel to start displaying an image.

Abstract: An electronic device includes a first circuit module and a second circuit module, wherein the first circuit module includes a write pointer generation circuit and a write data generation circuit for generating a write pointer and a write data; and the second circuit module includes a storage unit, a read pointer generation circuit and a comparator. The storage unit is used for storing the write data, the read pointer generation circuit is used for generating a read pointer, the comparator compares the write pointer and the read pointer to determine whether to read the write data from the storage unit, the write pointer and the write data are sent to the second circuit module through multiple wires, and a signal propagation time of the multiple wires is greater than one cycle of a clock signal used by the first circuit module.

Abstract: A multilane transmitter includes a plurality of transmitter lane circuits and a phase lock circuit. The phase lock circuit includes an oscillating circuit. The oscillating circuit is configured to provide clock signals corresponding to the transmitter lane circuits. The oscillating circuit includes a plurality of logic units. Clock receiving terminals of the transmitter lane circuits are coupled to an output terminal of one of the plurality of logic units.

Abstract: A video processing system includes a system processor circuit and a video processor circuit. The system processor circuit includes a graphic buffer and an open media acceleration layer. The graphic buffer is configured to store video data from a camera. The open media acceleration interface is configured to extract at least one data parameter associated with the video data. The video processor circuit is configured to receive the at least one data parameter, receive the video data from the graphic buffer according to the at least one data parameter, encode the video data according to the at least one data parameter to generate encoded data, and transmit the encoded data to the system processor circuit.

Abstract: The present invention discloses a Bluetooth mesh network system having wake-up management mechanism that includes a control node and low power nodes. The control node broadcasts a wake-up parameter setting packet at broadcast time spots based on a broadcast period. Each of the low power nodes receives the wake-up parameter setting packet to be operated in a wake-up management mode to configure a start time spot, a time length and a period interval length of a wake-up period that is synchronous among the low power nodes accordingly. The control node further transmits data corresponding to the low power nodes in the wake-up period and the low power nodes is operated in a wake-up state within the wake-up period to receive the data from the control node and is operated in a sleep state outside of the wake-up period.

Abstract: A Bluetooth communication system includes: a Bluetooth host device; and a Bluetooth device set which including a first member device and a second member device. The first member device transmits a device information of the first member device to the Bluetooth host device. The Bluetooth host device controls a display device to display a candidate device list, and to display a single device item in the candidate device list to represent the Bluetooth device set, but does not simultaneously display two device items in the candidate device list to represent the first member device and the second member device. The Bluetooth host device further establishes a connection with the first member device to conduct pairing procedure to generate a first cypher key after receiving a selection command. The first member device further establishes a connection with the Bluetooth host device to conduct pairing procedure to generate a second cypher key.

Abstract: A method for packet filtering in a network switch includes: utilizing an access control list circuit to filter received packets, wherein the access control list circuit compares header information of the received packets with an access control list to filter the received packets, where the access control list has at least one entry, and rule information in the entry includes only a portion of an IP address; and utilizing a routing circuit to further filter packets that pass the access control list circuit, wherein the routing circuit compares header information of the packets that pass the access control list circuit with a routing table to filter the packets, wherein the routing table has at least one entry, and rule information in the entry includes an entire IP address.

Abstract: A test circuit includes a scan chain and a wrapper chain. The wrapper chain shifts in a test pattern according a first clock. The scan chain is coupled to the wrapper chain via a logic combination of a circuit under test. The wrapper chain is configured to transmit the test pattern to the scan chain via the logic combination according to a second clock in a capture phase. The wrapper chain includes a first, a second wrapper cell, and an asynchronous register. The first wrapper cell sequentially shifts in two bits of the test pattern in the shift-in phase. The second wrapper cell shifts in the first bit of the test pattern in the shift-in phase. The asynchronous register conducts the first wrapper cell to the second wrapper cell in the shift-in phase, and latches the second wrapper cell in the capture phase.

Abstract: A transceiver includes a RF modulator, a filter circuit, a control circuit and a first DC offset compensation circuit. During a first calibration period, the control circuit controls the filter circuit to be connected to the RF modulator with a first phase sequence, such that the RF modulator outputs a first radio frequency signal. During a second calibration period, the control circuit controls the filter circuit to be connected to the RF modulator with a second phase sequence, such that the RF modulator outputs a second radio frequency signal. The second phase sequence is inverted with the first phase sequence. The control circuit is further configured to calculate a first DC offset generated from the filter circuit, and to control the first DC offset compensation circuit to compensate the first DC offset generated from the filter circuit.