Abstract: A detection circuit configured to detect whether timing violations occur in a target circuit. The target circuit is operated according a clock signal. The detection circuit includes a signal generation circuit, a first delay adjustable circuit, a second delay adjustable circuit, and a signal detector. The signal generation circuit is configured to generate a test signal. The first and second delay adjustable circuit are respectively configured to delay the test signal and clock signal to generate a first delay signal and a second delay signal according to the operating speed of the target circuit. The signal detector is configured to generate an indicating signal according to the first delay signal, the second delay signal, the test signal, and the clock signal. The indicating signal is configured to indicate whether an operating voltage of the target circuit causes a hold time violation of timing violations to occur in the target circuit.

Abstract: A Bluetooth voice communication system includes: a Bluetooth host device arranged to operably conduct voice communication with a remote device; a first Bluetooth member device arranged to operably generate a left-channel voice data according to sounds captured by a first sound receiving circuit, and arranged to operably utilize a first Bluetooth communication circuit to transmit the left-channel voice data to the Bluetooth host device; and a second Bluetooth member device arranged to operably generate a right-channel voice data according to sounds captured by a second sound receiving circuit, and arranged to operably utilize a second Bluetooth communication circuit to transmit the right-channel voice data to the Bluetooth host device. The Bluetooth host device generates a stereo voice data based on the left-channel voice data and the right-channel voice data, and utilizes a signal transceiver circuit to transmit the stereo voice data to the remote device.

Abstract: An audio processing apparatus and an audio processing method for dynamically adjusting an audio clock are provided. The audio processing apparatus includes a first interface, a buffer, a clock generator, a processor, and a second interface. The first interface receives audio data from the host. The buffer stores the audio data to generate a first audio packet and determines relationships between a data volume of the first audio packet and a first upper threshold and a first lower threshold. The second interface outputs the first audio packet and a clock signal to a codec apparatus. In response to the data volume of the first audio packet being less than the first lower threshold, the buffer outputs an underflow interrupt signal. In response to the data volume of the first audio packet being greater than the first upper threshold, the buffer outputs an overflow interrupt signal.

Abstract: A time-interleaved analog to digital converter includes first and second capacitor array circuits, first and second transfer circuits, a fine converter circuitry, and an encoder circuit. The capacitor array circuits sample an input signal and generate first residues according to first quantization signals. The first and second transfer circuits transfer first and second residues respectively. The fine converter circuitry performs a noise shaping signal conversion on the first and second residues to generate a second quantization signal. A turn-on time of the corresponding first transfer circuit is determined based on the coarse conversion corresponding to a first capacitor array circuit and the noise shaping signal conversion corresponding to a second capacitor array circuit to selectively bring forward a start time of the noise shaping signal conversion. The encoder circuit generates a digital output according to the first and the second quantization signals.

Abstract: A method of defense against cryptosystem timing attack such as Rivest-Shamir-Adleman (RSA) cryptosystem timing attack, an associated cryptosystem processing circuit and an associated electronic device are provided. The method may include: utilizing a point double calculation circuit to perform a plurality of point double calculation operations related to a predetermined cryptosystem; utilizing a point add calculation circuit to perform a plurality of point add calculation operations related to the predetermined cryptosystem; and in response to there being no need to perform any point add calculation operation related to the predetermined cryptosystem, utilizing a dummy point add calculation circuit to perform a dummy point add calculation operation to emulate a calculation time of performing the any point add calculation operation, without changing a calculation result before performing the dummy point add calculation operation.

Abstract: A delta-sigma modulator is provided. The delta-sigma modulator includes a multiplexer, a modulation circuit and a demultiplexer. The multiplexer is configured to receive a first analog signal and a second analog signal, and output an input signal. The first analog signal and the second analog signal are in different electrical forms, and the multiplexer is configured to select, in a time-division manner, the first analog signal or the second analog signal as the input signal SIN to be output. The modulation circuit is configured to modulate the input signal into a digital signal. The demultiplexer has a first output terminal and a second output terminal, and selects the first output terminal or the second output terminal in a time-division manner to output the digital signal.

Abstract: An audio dose monitoring circuit includes: a sound level measuring circuit arranged to operably generate multiple sound level values, wherein the multiple sound level values respectively correspond to the sound levels generated by an audio playback device at multiple time points or the sound levels received by a microphone at multiple time points; an audio dose calculating circuit coupled with the sound level measuring circuit and arranged to operably generate an audio dose value corresponding to a measuring period based on the multiple sound level values and contents of a weighting table; a control circuit coupled with the audio dose calculating circuit and arranged to operably compare the audio dose value with a dose threshold to determine whether to generate a control signal or not; and an indication signal generating circuit coupled with the control circuit and arranged to operably generate a corresponding indication signal according to the control signal.

Abstract: A transformer device includes a first and a second trace, a first and a second connection member, and a first input/output member. A second sub-trace of the first trace is coupled to a first sub-trace of the first trace at a first and a second area. The first connection member is coupled to the first and the second sub-trace. The first and a third sub-trace of the second trace are disposed in turn. A fourth sub-trace of the second trace is coupled to the third sub-trace at the first and the second area. The second and the fourth sub-trace are disposed in turn. The second connection member is coupled to the third and the fourth sub-trace. The first sub-trace includes first wires, and the first input/output member is coupled to the first wire which is located at an inner side among the first wires.

Abstract: A memory device includes a resistor and a controller chip. The controller chip includes a first controller, a second controller, a first set of input/output (I/O) circuits, a second set of I/O circuits, a first calibration circuit, a second calibration circuit, and an arbitration circuit. The first controller transmits a first controller calibration request. The second controller transmits a second controller calibration request. The arbitration circuit instructs the first calibration circuit to perform a first controller calibration on the first set of I/O circuits using the resistor in response to the first controller calibration request, and instructs the second calibration circuit to perform a second controller calibration on the second set of I/O circuits using the resistor in response to the second controller calibration request. A first time interval of performing the first controller calibration and a second time interval of performing the second controller calibrations are non-overlapping.

Abstract: The present disclosure discloses a clock and data recovery circuit. A sampling circuit performs burst mode over-sampling on an input analog data signal according to a sampling timing in a burst mode to generate over-sampling results. A selection circuit determines neighboring two of the over-sampling results having opposite logic states in the burst mode to select data edge sampling results and data center sampling results interlaced with each other and having the same time period with input analog data signal from the over-sampling results accordingly to be output sampling results. A phase detection circuit performs phase detection according to the output sampling result to generate a phase locking direction. A phase adjusting circuit adjusts the sampling timing of the sampling circuit according to the phase locking direction to track the input analog data signal.

Abstract: The present invention discloses an electrical discharge circuit having stable discharging mechanism is provided. A voltage division circuit generates a detection signal based on a voltage input terminal such that a first inverter outputs an inverted detection signal. First PMOS and NMOS circuits are coupled in series between a voltage input terminal and a ground terminal through a first terminal. Second PMOS and NMOS circuits are coupled in series between the voltage input terminal and the ground terminal through a second terminal. A first and a second PMOS control terminals are coupled to the second terminal and the first terminal respectively. A first and a second NMOS control terminals receive the inverted detection signal and the detection signal respectively. A second inverter receives an inverted boost detection signal from the second terminal and outputs a boost detection signal. AN ESD transistor is turned off due to the boost detection signal to discharge the voltage input terminal.

Abstract: A coding algorithm encodes consecutive frames of a video sequence and realizes distributed Gradual Decoding Refresh. The consecutive frames include a first frame, a second frame, and a third frame, and each frame is composed of (X+Y+Z) columns of coding tree units. The algorithm includes: coding X columns of the first frame in an intra coding manner and coding the other columns of the first frame in an inter coding manner and/or the intra coding manner; coding X columns of the second frame in the inter coding manner, coding Y columns of the second frame in the intra coding manner, and coding Z columns of the second frame in the inter and/or intra coding manner(s); and coding X and Y columns of the third frame in the inter coding manner, and coding Z columns of the third frame in the intra coding manner. The X/Y/Z columns (intra-coded columns) are inconsecutive.

Abstract: A dongle device and a firmware updating method are provided. The dongle device includes a connector, a communication module, a storage module, and a control module. The storage module is configured to store a device ID and a first image file. The control module is electrically connected to the connector, the communication module, and the storage module. The control module is configured to output an updating command to an electronic device through the connector, control the communication module to scan and to wirelessly receive a broadcast packet broadcasted by the electronic device, control the communication module to establish a wireless connection between the dongle device and the electronic device according to the broadcast packet, and use the first image file to update a firmware of the electronic device via the wireless connection. The updating command and the broadcast packet have the same device ID.

Abstract: A central processing unit includes a processing module and an output module. The processing module is configured to generate a task packet according to an execution task. The output module is configured to output the task packet to an I3C controller, such that the I3C controller executes the task packet to complete the execution task. The task packet includes a definition word and at least one data byte sequentially concatenated to the definition word. The definition word includes four setting bytes that are sequentially concatenated one another and respectively define a first write number for a first write operation, a second write number for a second write operation, a read number for a read operation, and a third write number for a third write operation. The execution task includes at least one of the first write operation, the second write operation, the read operation, and the third write operation.

Abstract: A method for establishing a variation model related to circuit characteristics for performing circuit simulation includes: performing first, second, third, and fourth Monte Carlo simulation operations according to a first netlist file and predetermined process model data to generate a first, a second, a third, and a fourth performance simulation results, respectively, where the first netlist file is arranged to indicate a basic circuit in a circuit system; and execute a performance simulation results expansion procedure according to the first, the second, the third, and the fourth performance simulation results to generate a plurality of performance simulation results to establish the variation model, for performing the circuit simulation to generate at least one circuit simulation result according to one or more performance simulation results among the plurality of performance simulation results, where the number of the plurality of performance simulation results is greater than four.

Abstract: A method for compressing images based on joint photographic experts group (JPEG) standard includes: compressing data of one or more first image blocks with a first compression level to produce compression data of the one or more first image blocks; adjusting the first compression level to obtain a second compression level according to at least one of a data size-related index regarding the compression data of the one or more first image blocks or a transmission-related index regarding transmission of the compression data of the one or more first image blocks; and compressing data of a second image block with the second compression level.

Abstract: A method of switching an operation mode of a first multi-link device includes the first multi-link device establishing a plurality of links to a second multi-link device, and the first multi-link device determining according to a channel condition whether to receive a plurality of streams via the plurality of links or via one of the plurality of links.

Abstract: A computing device includes: a storage circuit, for storing an arbitration interframe space (AIFS) time, at least one expected value of at least one backoff time, a preamble time, a short interframe space (SIFS) time and an acknowledgement (ACK) time; a first computing circuit, for computing a payload time according to a packet length and a packet rate; a second computing circuit, coupled to the storage circuit and the first computing circuit, for computing at least one packet transmission time according to the AIFS time, the at least one expected value of the at least one backoff time, the preamble time, the SIFS time, the ACK time and the payload time; and a third computing circuit, coupled to the second computing circuit, for computing a total packet transmission time according to the at least one packet transmission time and an estimated packet error rate.

Abstract: A signal transporting system, comprising: a signal transporting circuit, configured to receive an input signal to generate an output signal; and a signal timing adjusting circuit, configured to adjust an output timing of the output signal according to a signal pattern of the input signal.

Abstract: A data transmission apparatus includes a transmit-side circuit and a receive-side circuit. The transmit-side circuit belongs to a first clock domain, and is configured to store a plurality of input data. The receive-side circuit belongs to a second clock domain, and is configured to read a plurality of output data from the transmit-side circuit. The transmit-side circuit is configured to calculate a transmit-side parity value according to the plurality of input data. The receive-side circuit is configured to calculate a receive-side parity value according to the plurality of output data. The receive-side circuit is configured to compare the transmit-side parity value with the receive-side parity value to generate a control signal. The transmit-side circuit and the receive-side circuit are configured to reset, according to the control signal, a write pointer of the transmit-side circuit and a read pointer of the receive-side circuit.