Abstract: An integrated circuit (IC) applicable to performing system protection through dynamic voltage change may include a monitoring circuit, at least one power voltage generation circuit and a voltage adjustment circuit. The monitoring circuit monitors at least one security checking result of a security engine to determine whether at least one security event occurs. The at least one power voltage generation circuit generates at least one internal power voltage within the IC according to at least one input voltage received from outside of the IC, to provide the internal power voltage to at least one internal component of the IC. In response to occurrence of the at least one security event, the voltage adjustment circuit controls the at least one power voltage generation circuit to dynamically adjust the at least one internal power voltage, to control the internal power voltage randomly exceed predetermined voltage range thereof, thereby performing the system protection.

Abstract: An audio signal modulation and amplification circuit includes a common-mode electric potential controller, a carrier generator, and channel circuits. The common-mode electric potential controller is configured to generate one or more first common-mode electric potentials and second common-mode electric potentials. The carrier generator is adapted to receive the first common-mode electric potential to generate a carrier signal. Each of the channel circuits includes a filter, a comparison circuit, and a driving circuit. The filter is adapted to filter an input signal and generate a filtered signal based on a corresponding one of the second common-mode electric potentials. The comparison circuit is configured to compare the potential of the carrier signal with the potential of the filtered signal to generate a pulse-width modulation signal. The driving circuit is configured to be turned on or off in response to the pulse-width modulation signal to output a load driving signal.

Abstract: An electronic system includes a main chip, a non-volatile storage circuit, and a detector circuit. The main chip is configured to read first time of a clock circuit. The non-volatile storage circuit is coupled to the main chip. The main chip stores the first time into the non-volatile storage circuit. The detector circuit includes a first output terminal. The first output terminal is coupled to the main chip. When a cold boot event occurs, the main chip reads the first time from the non-volatile storage circuit, and determines a reason of the cold boot event according to the first time, a second time of the clock circuit, and a logic value at the first output terminal.

Abstract: A memory control circuit includes an access control circuit, a connection pad circuit, and a pad control circuit. The connection pad circuit includes a transceiver circuit and a receiver circuit. The transceiver circuit and the receiver circuit are connected to a memory through an external pad. The pad control circuit is connected between the access control circuit and the receiver circuit. The pad control circuit executes a read command, and receives data from the memory. The pad control circuit executes a write command or receives the data, the pad control circuit turns off the output of the receiver circuit. The access control circuit executes a power save command that the receiver circuit enters a power save mode. The pad control circuit decreases an operating current of the receiver circuit to minimum and forces an internal signal level of the receiver circuit. The receiver circuit enters a deep power save state.

Abstract: A system and a method for performing field programmable gate array (FPGA) prototype verification on a tested circuit are provided. The system includes a packet generator, a scrambling circuit, the tested circuit and a checking circuit, wherein the scrambling circuit, the tested circuit and the checking circuit are implemented on an FPGA. The packet generator outputs multiple standard packets, wherein a length of each standard packet falls within a standard range. The scrambling circuit generates multiple scrambled packets according to the multiple standard packets to the tested circuit, to make the tested circuit generate multiple output packets according to the multiple scrambled packets, wherein a length of any scrambled packet falls outside the standard range. The checking circuit verifies operations of the tested circuit according to the multiple scrambled packets and the output packets.

Abstract: A super resolution device and method are provided. The device comprises an input interface and a sharing layer calculator group. An image and a scaling signal are received by the input interface, wherein the scaling signal is configured to indicate to perform a double scaling operation or a quadruple scaling operation to the image. When the scaling signal indicates to perform the quadruple scaling operation, the sharing layer calculator group performs a plurality of convolution operations based on a first number of input channels and a first number of output channels. When the scaling signal indicates to perform the double scaling operation, the sharing layer calculator group performs the convolution operations based on a second number of input channels and a second number of output channels.

Abstract: A signal converting circuit includes a phase interpolator circuit and a bias voltage generation circuit. The phase interpolator circuit is configured to convert a plurality of input clock signals into an output clock signal according to a digital signal. The bias voltage generation circuit is electrically coupled to the phase interpolator circuit, is configured to generate a bias voltage according to a reference information and is configured to output the bias voltage to the phase interpolator circuit, so that the output clock signal has a predetermined phase corresponding to one of a plurality of bit configurations of the digital signal, wherein the reference information is relevant to a change of the phase interpolator circuit due to a temperature variation.

Abstract: A two-stage 4-phase clock buffer having a cascade of a first stage and a second stage, wherein: the first stage includes four p-channel oxide semiconductor transistors (PMOSTs) configured in a common-source ring topology to dispatch a first 4-phase clock, and four n-channel oxide semiconductor transistors (NMOSTs) configured in a common-source topology to control the first 4-phase clock in response to a second 4-phase clock; and, the second stage includes four NMOS transistors configured in a common-source ring topology to dispatch a third 4-phase clock, and four PMOS transistors configured in a common-source topology to control the third 4-phase clock in response to the first 4-phase clock.

Abstract: An method of integrating an oscillator includes incorporating a main inductor and a main capacitor for establishing an oscillation; incorporating two cross-coupling NMOST and two cross-coupling PMOST for sustaining the oscillation; incorporating a first auxiliary inductor and a first auxiliary capacitor for suppressing a noise of the two cross-coupling NMOST; incorporating a second auxiliary inductor and a second auxiliary capacitor for suppressing a noise of the two cross-coupling PMOST; laying out the main inductor symmetrically with respect to a plane of symmetry; laying out the first auxiliary inductor as a parallel connection of two halves that are inside the main inductor and symmetrical with respect to the plane of symmetry; and laying out the second auxiliary inductor as a parallel connection of two halves that are inside the main inductor in a close proximity to the first auxiliary inductor and symmetrical with respect to the plane of symmetry.

Abstract: An IC test method, comprising: electrically connecting a circuit board to a first IC; generating a first test signal to test the first IC; electrically connecting the circuit board to a first adaption board, and electrically connecting a second IC to the first adaption board, wherein a first connection mechanism between the first IC and the circuit board and a second connection mechanism between the second IC and the circuit board are different; and generating a second test signal to test the second IC by the control IC.

Abstract: A judgment system, an electronic system, a judgment method, and a display method are provided. The judgment method includes: receiving an image by a feature acquisition module and obtaining a first key point coordinate, a second key point coordinate, and a size of a face box of a user by the feature acquisition module based on the image; and performing following steps by a judgment module: obtaining a judgment value based on an ordinate of the first key point coordinate, an ordinate of the second key point coordinate, and a size of the face box; and sending a rotation signal in response to that the judgment value satisfies a rotation condition.

Abstract: A radio frequency (RF) transceiver circuit includes a transmission circuit, a reception circuit, and a pre-distortion processing circuit. The transmission circuit is arranged to generate a transmission signal, wherein the transmission signal is transmitted to an antenna through a first pin. The reception circuit is arranged to receive a reception signal through a second pin. The pre-distortion processing circuit is arranged to receive a feedback signal through a third pin, and calculate distortion information of the transmission signal according to the feedback signal in order to generate and transmit a compensation signal to the transmission circuit for performing a pre-distortion compensation operation, wherein the feedback signal is generated according to a coupling signal of the transmission signal.

Abstract: A method of identifying the type of a memory card is provided for identifying the type of a secure digital (SD) card. The pin number of the SD card complies with an SD card specification formulated by the Secure Digital Association. The method includes the following steps: performing a legacy SD card initialization procedure on the SD card; and sequentially determining whether the SD card is an SD Express card, an Ultra High Speed type II (UHS-II) SD card, or a legacy SD card.

Abstract: An electronic device capable of accessing a memory and a data writing method are provided. The electronic device includes a processing unit, a bus, and a memory controller. The processing unit includes a bus interface control circuit, and the processing unit generates a first write command through the bus interface control circuit according to a memory access command. The memory access command contains a first memory address and a target value, and the first write command contains the first memory address and the target value. The bus is coupled to the bus interface control circuit and configured to generate a second write command according to the first write command. The second write command contains a second memory address and the target value. The memory controller is coupled to the bus and configured to write the target value into the memory according to the second memory address.

Abstract: A solid-state drive (SSD) controller is operable to determine whether M supply voltage(s) supplied to a NAND flash memory is correct. The SSD controller includes: a voltage detector configured to receive the M supply voltage(s) and thereby generate a detection result, wherein the M is a positive integer; a voltage inquiry module configured to output an inquiry signal to the NAND flash memory and thereby receive a response signal from the NAND flash memory, and configured to generate an inquiry result according to the response signal, wherein the inquiry result indicates M specified supply voltage(s) applicable to the NAND flash memory; and a voltage decision module configured to receive the detection result and the inquiry result, and configured to determine whether the M supply voltage(s) is/are equivalent to the M specified voltage(s) according to the detection result and the inquiry result and thereby generate a decision result.

Abstract: A card reader and a controller thereof, and a method are provided. The card reader includes a storage device and the controller, wherein the controller is coupled to the storage device. The storage device is configured to store specific identification data of a specific memory device. The controller is configured to receive identification data of the external memory device plugged into the card reader, and determine whether the external memory device is the specific memory device according to the identification data and the specific identification data, to generate a determination result. More particularly, the controller may control whether to open permission of at least one function according to the determination result.

Abstract: A semiconductor device includes a plurality of leads, a lower die, a plurality of bumps, a plurality of flip-chip solder pads, an upper die, a plurality of metal connecting pillars, and a metal wire bonding layer. Each of the leads has a first end and a second end. The leads include a plurality of first leads, a plurality of second leads, and a plurality of third leads. The first ends of the first leads are defined as a die-bonding region. The lower die is correspondingly disposed on the die-bonding region. The flip-chip solder pads are respectively disposed on the first ends of the first leads. The upper die is disposed on the lower die. The metal connecting pillars respectively stand on the first ends of the second leads. The metal wire bonding layer is disposed between the upper die and the lower die.

Abstract: A linearity test system for a chip, a linearity signal providing device, and a linearity test method for the chip are provided. The linearity test method for the chip includes steps as follows: providing a reference clock signal and a receiver input signal to a chip under test, wherein the reference clock signal and the receiver input signal have a phase difference in time domain; and determining a linearity of a phase interpolator of the chip under test based on a plurality of phase signals of the chip under test corresponding to the reference clock signal and the receiver input signal.

Abstract: An integrated circuit includes a plurality of control circuits and a resource controller. Each of the control circuits is configured to send a work request, execute a work procedure according to an authorization code corresponding to the work procedure, and generate a completion signal after the work procedure is completed. The resource controller includes a storage circuit stores a plurality of index values; a processor circuit updates, according to each of the completion signals, a status of the index value associated with the authorization code corresponding to the work procedure; and a conversion circuit configured to, in response to each of the work requests, output, when a status of at least one of the index values is resource-available, an authorization code associated with one index value whose status is resource-available.

Abstract: A method for performing multi-system log access management and an associated SoC IC are provided. The method may include: utilizing multiple partial circuit of at least one processor in the SoC IC to run multiple systems, respectively; utilizing a first partial circuit to execute at least one first log management procedure, to configure at least one memory into multiple ring buffers, to record a set of first logs of a first system running on the first partial circuit into a first ring buffer, and to write multiple sets of logs respectively stored in the multiple ring buffers into a file system; and utilizing at least one second partial circuit to execute at least one second log management procedure, to record at least one set of second logs of at least one second system running on the at least one second partial circuit into at least one second ring buffer.