Abstract: A method for resuming topology of a single loop network and a network switch system are provided. The network switch system includes one or more first network switches each having a first port and a second port and a second network switch having a third port and a fourth port. When the first port of one of the first network switches is abnormal, a recovery control frame is transmitted through the second port. The second network switch sets the third port in a disabled state to an enabled state. When the abnormal port is resumed, the first network switch transmits a block control frame through the second port. The second network switch sets the third port in the enabled state to the disabled state and transmits a forward control frame through the fourth port. The first network switch sets the first port in the disabled state to the enabled state.

Abstract: An audio system is proposed, dynamically playing optimized audio signals based on user position. A sensor circuits dynamically senses a target space to generate field context information. First speaker and second speaker are arranged for audio playback. A host device recognizes a user from the field context information, determines the user position corresponding to the target space, and adaptively assigns the user position as a target listening spot. A sensor circuit contains a camera capturing an ambient image out of the target space. A recognizer circuit analyzes the ambient image to obtain from the target space, the location, size and acoustic attribute information of an ambient object, allowing the control circuit to accordingly perform an object-based compensation operation on the target listening spot to generate optimized first channel audio signal and second channel audio signal.

Abstract: A finger-type semiconductor capacitor array layout includes a first conductive structure and a second conductive structure. The first conductive structure includes longitudinal first conductive strips and lateral power supply strips. The second conductive structure includes longitudinal second conductive strips and P lateral power supply strip(s). The longitudinal first conductive strips and the longitudinal second conductive strips are alternately disposed in a first integrated circuit (IC) layer; and the longitudinal first conductive strips include a first row of strips and a second row of strips. The lateral power supply strips are located in a second IC layer, and coupled to the first and second rows of strips through vias. The P lateral power supply strip(s) is/are located in the second IC layer, and include(s) a first-capacitor-group power supply strip that is coupled to K strip(s) of the longitudinal second conductive strips through K via(s). The P and K are positive integers.

Abstract: The application discloses a WiFi station and an associated passive scanning method, including receiving an RF signal within a specific frequency band to generate a baseband signal; detecting whether the baseband signal includes a first preamble corresponding to a first channel and generating a first detecting result accordingly; detecting whether the baseband signal includes a second preamble corresponding to a second channel and generating a second detecting result accordingly; according to the first detecting result and the second detecting result, determining to use a center frequency of the first channel or a center frequency of the second channel to perform frequency shifting on the baseband signal, to generate the frequency-shifted baseband signal.

Abstract: An electronic device used in a wireless communication network is wirelessly coupled between an access point device and a station device, and it comprises a receiver circuit, a decryption circuit, an address swap circuit, an encryption circuit, and a transmitter circuit. The receiver circuit receives a wireless packet. The decryption circuit decrypts the received wireless packet to generate a decrypted wireless packet. The address swap circuit changes information of at least one MAC address recorded in a MAC header of the decrypted wireless packet to generate an address-swapped packet so as to disguise itself as the access point device or the station device. The encryption circuit encrypts the address-swapped packet to generate an encrypted packet. The transmitter circuit sends the encrypted packet into the air.

Abstract: A method for performing a power disturbing operation to reduce a success rate of cryptosystem power analysis attack, an associated cryptosystem processing circuit and an associated electronic device are provided.

Abstract: A content channel generation device comprises a resource unit assignment circuit, for assigning scheduled station(s) as node(s) of a full binary tree according to a search algorithm; a node computing circuit, for determining first node connection information of the full binary tree, and to determine second node connection information of a smallest full binary tree according to a smallest binary tree algorithm and the first node connection information; a load balance circuit, for determining user field numbers corresponding to content channels according to a load balance function and the second node connection information; a user field generation circuit, for generating a traversal result of the smallest full binary tree according to a traversal algorithm and the second node connection information, and for generating user fields corresponding to the content channels according to the traversal result, to generate the content channels.

Abstract: A masking circuit of a content addressable memory (CAM) includes a masking control circuit and a level control circuit. The masking control circuit generates a masking signal according to a word line (WL) signal and a write enablement (WE) signal. When both the WL and WE signals are at a first level, the masking signal is a first masking signal; when they are at different levels respectively, the masking signal is a second masking signal. The level control circuit generates a level control signal according to the masking signal for determining whether to pull a voltage level of a match line of the CAM to a predetermined level. When the masking signal is the first masking signal, the level control circuit pulls the voltage level to the predetermined level; and when the masking signal is the second masking signal, the level control circuit does not interfere in the voltage level.

Abstract: A lead frame adapted to be applied to a QFN package structure is provided. The lead frame includes a die-bonding region and a plurality of leads. The die-bonding region is configured to allow a die to be disposed. The leads include a first lead and a plurality of second leads. The first lead includes a first edge pin, an internal pin, and a first extension part. The internal pin is connected to a bottom surface of one of two ends of the first extension part. The first edge pin is connected to a bottom surface of the other end of the first extension part. Each of the second leads includes a second edge pin and a second extension part. The second edge pin is connected to a bottom surface of one of two ends of the second extension part.

Abstract: A signal adjusting circuit and a receiving end circuit using the same are provided. The signal adjusting circuit is adapted to a peak detector, and includes a first amplifier and a first feedback circuit. The first amplifier receives a first input signal, and amplifies the first input signal to output a first output signal. The first feedback circuit is connected between a first input terminal and a first output terminal of the first amplifier, and is configured to determine a first gain of the first output signal. The peak detector is connected to a first output node of the first feedback circuit, so as to receive a first detection signal and detect a peak value of the first detection signal. The peak detector has a predetermined power input range, and the first feedback circuit keeps the first detection signal within the predetermined power input range.

Abstract: An inductor device includes a first wire, a second wire, and a third wire. The first wire includes a plurality of first sub-wires. The second wire includes a plurality of second sub-wires. The sequence of the first sub-wires and the second sub-wires is that at least two first sub-wires of the first sub-wires and at least one second sub-wires of the second sub-wires are disposed to each other in an interlaced manner. The third wire is disposed adjacent to at least two first sub-wires of the first sub-wires.

Abstract: A current load circuit for testing a power supply circuit includes a control circuit and a load generation circuit. The control circuit is configured to generate a reset signal according to a clock signal. The load generation circuit is coupled to the control circuit and has several load configurations. The load generation circuit is configured to provide one of the load configurations as a current load of the load generation circuit according to the clock signal and the reset signal and receive a portion of the supply current provided by the power supply circuit according to the current load to generate an indication signal for indicating a performance of the power supply circuit.

Abstract: An electronic device capable of accessing a memory card is provided. The electronic device includes a circuit board, a processing unit, a memory card slot, and a memory card access module. The processing unit is disposed on the circuit board. The memory card slot is disposed on the circuit board, allows the insertion of the memory card, and is coupled to the processing unit through a first signal line. The memory card access module is disposed on the circuit board for accessing the memory card. The memory card access module is coupled to the processing unit through a second signal line and coupled to the memory card slot through a third signal line and a fourth signal line. The first signal line, the second signal line, and the third signal line conform to the standard of a signal transmission interface.

Abstract: A CEC system, comprising: a first IC, comprising a first pin and an anti-leakage circuit electrically coupled to the first pin; and a second IC, comprising a second pin electrically coupled to the first pin. The first IC or the second IC is configured to provide a CEC function. Thereby software can be used to simulate CEC functions to increase the number of CEC function sets without increasing hardware costs, to increase the application scope of the CEC system.

Abstract: An testing method includes following operations: generating, by a signal generator, a multi-tone signal; transmitting, by the signal generator, the multi-tone signal to an input terminal of an under-test device; measuring, by a spectrum analyzer, the input terminal of the under-test device and an output terminal of the under-test device to acquire a plurality of input ripple intensities corresponding to a plurality of frequencies and acquire a plurality of output ripple intensities corresponding to the frequencies; and generating, by a control device, a plurality of power supply rejection ratios corresponding to the frequencies according to the input ripple intensities and the output ripple intensities.

Abstract: A signal generating circuit and a signal generating method are provided. The signal generating circuit includes a first synchronization circuit configured to synchronize a beacon signal and a first signal edge of a clock signal to generate a first synchronization signal; a frequency dividing circuit configured to receive the clock signal and perform frequency division operation on the clock signal to generate a frequency division signal, wherein the duty cycle of the frequency division signal is 50%; a second synchronization circuit configured to receive the first synchronization signal and the frequency division signal and synchronize the first synchronization signal and a second signal edge of frequency division signal to generate a second synchronization signal; and a synthesis circuit configured to receive the second synchronization signal and the frequency division signal and perform AND operation on the second synchronization signal and the frequency division signal to output full-cycle signals.

Abstract: The present invention discloses an electrical discharge circuit having stable discharging mechanism. A voltage-dividing circuit generates a detection signal such that a first inverter outputs an inverted detection signal. A first PMOS and a first NMOS are coupled through a first terminal between the voltage input terminal and a ground terminal. A second NMOS is coupled between a second terminal and the ground terminal. A first PMOS control terminal is coupled to the second terminal. A first and a second NMOS control terminals respectively receive the inverted detection signal and the detection signal. A resistor and a capacitor are coupled through the control terminal coupled to the second terminal and between the voltage input terminal and the ground terminal. A second inverter receives an inverted boosted detection signal from the control terminal to output a boosted detection signal to control an electrostatic discharge MOS to discharge the voltage input terminal.

Abstract: A capacitor structure, including a transistor structure, a first metal conductive structure and a second metal conductive structure, is provided. The transistor structure includes a first ladder-shaped frame of a polycrystalline silicon layer and multiple first metal strips of a first metal layer. The first ladder-shaped frame is electrically isolated from the multiple first metal strips, and encircles a part of the multiple first metal strips. The first ladder-shaped frame forms a gate of the transistor structure. The multiple first metal strips form a drain and a source of the transistor structure. The first metal conductive structure is substantially overlapped with the first ladder-shaped frame. The second metal conductive structure is electrically connected to the multiple first metal strips, in which the second metal conductive structure is disposed across and electrically isolated from the first ladder-shaped frame and the first metal conductive structure.

Abstract: A coordinate generation system, a coordinate generation method, a computer readable recording medium with stored program, and a non-transitory computer program product are provided. The coordinate generation system includes processing units and a neural network module. The processing units are configured to obtain four vertex coordinates of an image. The vertex coordinates include first components and second components. The processing unit is configured to perform the following steps: obtaining first vector based on the first components of the four vertex coordinates and repeatedly concatenating the first vector so as to obtain a first input; obtaining second vector based on the second components of the four vertex coordinates and repeatedly concatenating the second vector so as to obtain a second input; and obtaining first output coordinate components and second output coordinate components of output coordinates based on the first input, the second input, and parameters of the neural network module.

Abstract: An analysis method configured to analyze original signals on an auxiliary channel of DisplayPort between a transmitter and at least one receiver, includes: receiving a first original signal of the original signals; dividing the first original signal to obtain a DPCD address and a first data; storing the first data according to the DPCD address; determining whether the first data is a redundant signal; when the first data is not the redundant signal, analyzing the first data; and displaying a topology of the at least one receiver. The operation of analyzing the first data includes generating the topology of the at least one receiver.