Abstract: A successive approximation register analog to digital converter includes a sampling circuitry, a comparator circuit, and a controller circuitry. The sampling circuitry generates first and second signals according to a sampled signal. The comparator circuit compares the first signal with the second signal to generate first decision signals. The controller circuitry generates digital codes according to the first decision signals, and controls the comparator circuit to perform comparisons repeatedly to generate second decision signals, in order to generate a digital output according to the digital codes, a statistical noise value, and the second decision signals.

Abstract: The present invention discloses a DAC method having signal calibration mechanism. A first conversion circuit generates a first analog signal according to an input digital signal. A second conversion circuit generates a second analog signal according to the input digital signal and a pseudo-noise digital signal. An echo transmission circuit processes a signal on an echo path to generate an echo signal. A first and a second calibration circuits generate a first and a second calibration signals. A calibration parameter calculation circuit performs calculation according to a difference between the echo signal and a sum of the first and the second calibration signals and related path information to generate a first and a second offsets. The first and the second calibration circuits converge first and second response coefficients and update a first and a second codeword offset tables according to the first and the second offsets.

Abstract: The present invention discloses a printed dual band antenna that includes a primary radiation portion and a parasitic radiation portion. The primary radiation portion is configured to perform signal transmitting and receiving based on a first resonant frequency and a second resonant frequency. The parasitic radiation portion is disposed on a neighboring side of the primary radiation portion, distanced from the primary radiation portion by a distance and electrically isolated from the primary radiation portion. The parasitic radiation portion couples to and resonates with the primary radiation portion to perform signal transmitting and receiving based on the second resonant frequency. The parasitic radiation portion is a grounded monopole parasitic antenna.

Abstract: An inductor device includes a first inductor and a second inductor. The first inductor has a first winding and a second winding. The second inductor has a third winding and a fourth winding, and the second inductor is disposed adjacent to the first inductor, and the second inductor is coupled to the first inductor in an interlaced manner.

Abstract: The present invention discloses an isolation circuit having test mechanism. An isolation circuit component performs signal transmission when a signal that a control terminal receives has an enabling state and performs signal isolation when the signal has a disabling state. The test circuit includes a multiplexer and a control circuit. Under a shifting operation state in a test mode, the control circuit controls the multiplexer to select an operation input terminal to receive and output an isolation control signal having the enabling state to the control input terminal. Under a capturing operation state in the test mode, the control circuit controls the multiplexer to select a test input terminal to receive and output the test signal to the control input terminal. The control circuit further determines whether the isolation circuit performs signal transmission or signal isolation according to the signals at the data input terminal and the data output terminal.

Abstract: A test circuit for testing a memory is provided. The input of the memory is coupled to a register, and the register is coupled to a logic circuit. The test circuit includes a first test register group, a second test register group, a first multiplexer, and multiple second multiplexers. The first test register group includes at least one test register. The second test register group includes at least one test register. The first multiplexer is coupled between the first test register group and the register. The second multiplexers are coupled between the second test register group and the register.

Abstract: A power supply management device includes an internal power supply circuit, switches, a comparator circuit, and a control circuit. The internal power supply circuit is configured to output a first supply voltage to a node. The switches are coupled between the node and a plurality of first circuits. The comparator circuit is configured to compare a voltage on the node with a reference voltage when the node does not receive the first supply voltage to generate a flag signal. The control circuit is configured to determine whether the node receives a second supply voltage from an external power supply circuit according to the flag signal. If the node receives the second supply voltage, the control circuit is further configured to turn off the internal power supply circuit and gradually turn on the switches, in order to provide the second supply voltage to the first circuits via the switches.

Abstract: Disclosed is a sorting device configured to sort N numbers with N rounds of sorting processes from a first round sorting process to an Nth round sorting process and obtain N-rounds sort results from a first-round sort result to an Nth-round sort result, wherein at least two pairs of numbers of the N numbers are sorted in each of the N rounds of sorting processes concurrently, a Kth-round sort result is dependent on a (K?1)th-round sort result, the Nth-round sort result is the N numbers in a descending/ascending order, and the N is an integer greater than two. The sorting device includes sorting circuits and duplicating circuits that are selectively used for each of the N rounds of sorting processes. Each sorting circuit is configured to sort two numbers and obtain the collating sequence of the two numbers. Each duplicating circuit is configured to output a number it received.

Abstract: A receiver decoding apparatus includes a first receiver decoder, a demultiplexer, a first receiver encoder and a second receiver decoder. The first receiver decoder decodes a plurality of N-bit code words received from a transmitter encoding apparatus to generate a plurality of I-bit code words, wherein N and I are both positive integers and N is not equal to I. The demultiplexer alternately deinterleaves and assigns the plurality of I-bit code words to a plurality of output terminals of the demultiplexer. The first receiver encoder encodes a plurality of outputs of the output terminals of the demultiplexer to a fifth digital signal comprising a plurality of J-bit code words and a sixth digital signal comprising a plurality of J-bit code words, wherein J is a positive integer and not equal to I. The second receiver decoder decodes the fifth digital signal and the sixth digital signal.

Abstract: A digital circuit device includes a power supply circuitry, a digital circuitry, a digital circuitry, and a protection circuitry. The power supply circuitry is configured to output a supply voltage. The digital circuitry is configured to be driven by the supply voltage, and is configured to perform at least one operation according to a first clock signal. The protection circuitry is configured to generate the first clock signal according to at least one of a voltage drop of the supply voltage and a load signal sent from the digital circuitry.

Abstract: The present invention discloses a communication apparatus having feedback calibration mechanism. A signal transmission circuit generates a RF analog signal according to a digital signal. A signal amplifying circuit amplifies the RF analog signal to generate an amplified analog signal. A LC impedance matching circuit transmits the amplified analog signal to the antenna to perform transmission. A feedback calibration circuit includes a feedback inductive circuit and a calibration circuit. A feedback inductive circuit is inductively coupled to the LC impedance matching circuit to receive the amplified analog signal to generate a feedback signal. A calibration circuit determines a distorted amount of the feedback signal relative to the RF analog signal to modify an operation parameter of at least one of the signal transmission circuit and the signal amplifying circuit to decrease the distorted amount.

Abstract: A device is provided that includes a first memory and a second memory and an accessing circuit. Actual addresses of the first memory and the second memory alternately correspond to reference addresses of a processing circuit. The accessing circuit is configured to perform the steps outlined below. A read command corresponding to a reference read address is received from the processing circuit to convert the reference read address to an actual read address of the first memory and the second memory. A first read data is read from a first one of the first memory and the second memory according to the actual read address and a second read data is prefetched from a second one of the first memory and a second memory according to a next first read address simultaneously.

Abstract: A method and circuit for controlling the compensation for channel mismatches are used in an electronic device which includes a signal transmission circuit or a signal receiving circuit that have two channels. The electronic device further includes a channel mismatch compensation circuit. The method includes: (A) determining a frequency of a test signal; (B) causing the test signal to pass through the signal transmission circuit or the signal receiving circuit, and measuring an image signal; (C) adjusting a compensation parameter of the channel mismatch compensation circuit to change an amplitude of the image signal; (D) determining, according to the amplitude of the image signal, a target compensation parameter of the channel mismatch compensation circuit, the target compensation parameter corresponding to the frequency of the test signal; (E) repeating steps (A) to (D) to obtain multiple target compensation parameters; and (F) determining a compensation mechanism based on the target compensation parameters.

Abstract: A power supply circuit includes a first regulator and a second regulator. The first regulator is configured to generate a first output signal according to an input signal. A voltage value of the first output signal decreases according to the input signal and a first voltage threshold value at a power-off stage. The second regulator is configured to be enabled according to the first output signal to generate a second output signal according to the input signal. A voltage value of the second output signal decreases according to the input signal and a second voltage threshold value at the power-off stage. The second voltage threshold value is greater than the first voltage threshold value.

Abstract: A pipeline analog to digital converter includes converter circuitries and a calibration circuitry. The converter circuitries sequentially convert an input signal into a plurality of first digital codes, in which a first converter circuitry in the converter circuitries is configured to perform a quantization according to a first signal to generate a first corresponding digital code in the first digital codes, and the first signal is a signal, which is processed by the first converter circuitry, of the input signal and a previous stage residue signal. The calibration circuitry combines the first digital codes to output a second digital code, detects whether the quantization is completed to generate control signals, and determines whether to set the second digital code to be a second corresponding digital code in predetermined digital codes according to the control signals.

Abstract: A data processing apparatus including a memory circuit and a data accessing circuit is provided, in which the memory circuit includes multiple cache ways configured to store data. In response to a first logic state of an enabling signal, if a tag of an address of an access requirement is the same as a corresponding tag of the multiple cache ways, the data accessing circuit determines that a cache hit occurs. In response to a second logic state of the enabling signal, if the address is within one or more predetermined address intervals specified by the data accessing circuit, the data accessing circuit determines that the cache hit occurs, and if the address is outside the one or more predetermined address intervals, the data accessing circuit determines that a cache miss occurs.

Abstract: A television system with a network function is disclosed. The television system includes several client devices and a server device. The several client devices are configured to store and transmit the client information. The client information includes channel information and several positions of the several client devices. The server device is communicatively connected to the several client devices and is configured to receive the client information, to integrate the client information so as to generate integrated information, and to transmit the integrated information to the several client devices. The several client devices are further configured to confirm the several integrated information so as to update the several client information.

Abstract: A bootstrapped switch includes a first transistor, a second transistor, a first capacitor, three switches, and a switch circuit. The switch circuit includes a first switch, a second switch, a second capacitor, and an inverter circuit. The first transistor receives the input voltage and outputs the output voltage. The first terminal of the second transistor receives the input voltage, and the second terminal of the second transistor is coupled to the first terminal of the first capacitor. The control terminal of the first switch receives a clock. The second switch is coupled between the control terminal of the first transistor and the first switch. The input terminal of the inverter circuit is coupled to the control terminal of the first switch. The second capacitor is coupled between the control terminal of the first transistor and the output terminal of the inverter circuit.

Abstract: The present disclosure provides an image SoC, an image capturing system including the same, and an image capturing method. The SoC includes a memory and a controller. The controller is configured to: read process data stored in the memory; perform an image sensor initialized process to start an image sensor according to the process data and to control the image sensor to capture a first image; after performing the image sensor initialized process, perform a program loader to load an image processing program into a non-read only memory according to the process data; and perform the image processing program to receive the first image.

Abstract: An amplifying circuit including a first gain circuit, a second gain circuit, a Miller capacitor, a positive feedback circuit and a feedforward gain circuit. The second gain circuit is configured to receive a first gain signal from the first gain circuit and generate a second gain signal. The Miller capacitor, the positive feedback circuit and the feedforward gain circuit are electrically coupled between an input terminal and an output terminal of the second gain circuit. The positive feedback circuit is configured to feedback the signal of the output terminal of the second gain circuit to the input terminal of the second gain circuit. The feedforward gain circuit is configured to amplify the first gain signal to output a third gain signal to the output terminal of the second gain circuit.