Abstract: An analog-to-digital converter, configured to convert an input signal into an n bits digital output signal, includes a capacitor module, a control signal generation unit, a comparator, and a register. The capacitor module is configured to receive the input signal at a sampling phase in a normal mode, and to generate a first sampling signal and a second sampling signal according to the input signal in a conversion phase. The control signal generation unit is configured to adjust the first sampling signal or the second sampling signal in the conversion phase. In the normal mode, the comparator is configured to compare the first sampling signal and the second sampling signal in the conversion phase to generate n comparison signals. The register is configured to store the n comparison signals as the digital output signal, and output the digital output signal in the normal mode.

Abstract: The present invention provides a hardware setting device and hardware setting method thereof. The hardware setting device is configured to: boot an operating system; retrieve at least one hardware setting corresponding to a peripheral device from a pre-boot memory; and configure the peripheral device according to the at least one hardware setting.

Abstract: An integrated transformer includes a first and second inductors. The first inductor includes a first and second windings. The second inductor includes a third and fourth windings. The first, second, third and fourth windings have a first, second, third and fourth outer turn, respectively. At least one segment of the first (or second) outer turn substantially overlaps at least one segment of the third (or fourth) outer turn. The first and second outer turns are connected through a first segment and a first trace that cross each other, and the third and fourth outer turns are connected through a second trace and a second segment that cross each other. The first trace and the second segment are on the first metal layer, and the first segment and the second trace are on the second metal layer different from the first metal layer.

Abstract: A method performed by a slave device to obtain a host memory address includes: inquiring a description list to obtain information of an allocated memory of a host; dividing the allocated memory into N storage spaces according to the information; using a first memory space of the N storage spaces to store a first level look-up table indicating physical addresses of the N storage spaces; dividing the first memory space into M storage spaces; storing a second level look-up table in the slave device to indicate physical addresses of the M storage spaces; inquiring the second level look-up table according to a logical address and obtaining a first index indicating a physical address of one of the M storage spaces; and inquiring the first level look-up table according to the first index and obtaining a second index indicating a physical address of one of the N storage spaces.

Abstract: The present invention discloses a power amplification apparatus having a digital pre-distortion mechanism that includes a digital pre-distortion circuit and a power amplifier. The digital pre-distortion circuit receives an original digital signal having an original real part and an original imaginary part. When a first one and a second one of the original real part and the original imaginary part are a low state voltage level and a high state voltage level, the digital pre-distortion circuit outputs a first and a second voltage levels equivalent to the low state voltage level as a first pre-distortion part and directly outputs the second one of the original real part and the original imaginary part as a second pre-distortion part to generate an input signal having an input real part and an input imaginary part each corresponding to one of the first pre-distortion part and the second pre-distortion part. The power amplifier receives the input signal to perform power amplification to generate an output signal.

Abstract: The present application provides a method for calibrating a transmitter. The transmitter includes an oscillator, a first signal path, and a second signal path. The first signal path and the second signal path include a first calibration unit preceding a first low pass filter and a second low pass filter, and a second calibration unit succeeding the first low pass filter and the second low pass filter. The calibration method includes: by configuring the first calibration unit and the second calibration unit and sending a transmission signal, and performing frequency analysis upon the transmission signal to obtain a frequency analysis result, to generate an optimized first compensation value for the first calibration unit and an optimized second compensation value for the second calibration unit.

Abstract: The present invention discloses a signal relay apparatus having frequency calibration mechanism that includes a clock generation circuit, a frequency generation circuit, a clock measuring circuit, a frequency adjusting circuit and a transmission circuit. The clock generation circuit generates a source clock signal. The frequency generation circuit receives the source clock signal and generates a target frequency signal according to a conversion parameter. The clock measuring circuit measures a first frequency offset of a source frequency relative to a first predetermined frequency according to an external reference clock signal. The frequency adjusting circuit adjusts the conversion parameter according to the first frequency offset when the first frequency offset is not within a first predetermined range such that a second frequency offset of a target frequency relative to a second predetermined frequency is within a second predetermined range.

Abstract: A data conversion device includes a storage circuit and a frequency tuning circuit. The storage circuit is configured to store a pixel data in a high definition multimedia interface (HDMI) signal according to a first clock, and output an image data according to a second clock. The frequency tuning circuit is configured to adjust the second clock according to a control signal and the second clock in the HDMI signal, and transmit the adjusted second clock to the storage circuit.

Abstract: A signal processer is configured to decrease total harmonic distortion plus noise of an output signal generated from an input signal. The signal processer includes a mixer, a pulse-width modulator, a power stage circuit, and a feedback circuit. The mixer is configured to mix the input signal and a feedback signal to generate a mixed signal. The pulse-width modulator is configured to module the mixed signal to generate a modulated signal and output the modulated signal from an output terminal of the pulse-width modulator. The power stage circuit is configured to amplify the modulated signal to generate the output signal and output the output signal from an output terminal of the power stage circuit. The feedback circuit is configured to generate a feedback signal selectively according to the modulated signal or the output signal.

Abstract: The present disclosure discloses an image flicker detection method that includes the steps outlined below. An image retrieving is performed to retrieve a current image. A current variation ratio between first rows of pixels of the current image and second rows of pixels in a previous image is calculated. When both the current variation ratio and a previous variation ratio are determined to be larger than a ratio threshold, a detected flicker number is incremented. When the detected flicker number is determined to be larger than a flicker number threshold, a flicker condition is determined to occur. When the detected flicker number is determined to be not larger than the flicker number threshold, the current image becomes the previous image and the current variation ratio becomes the previous variation ratio such that a next image becomes the current image to repeat the above steps.

Abstract: A transceiver includes a first digital-to-analog converter (DAC), a second DAC, and a timing control module. In a calibration mode, the first DAC transmits a transmitting signal; the second DAC transmits an echo cancellation signal; and the timing control module, according to an echo signal of the transmitting signal and the echo cancellation signal, obtains a timing offset therebetween, and generates a first timing control signal and a second timing control signal to the first DAC and the second DAC according to the timing offset, respectively. The first DAC adjusts a transmission delay of transmitting the transmitting signal according to the first timing control signal, and/or the second DAC modifies a transmission delay of transmitting the echo cancellation signal according to the second timing control signal.

Abstract: A method for calibrating currents includes performing a first sorting operation on a plurality of first current sources according to current levels generated by the first current sources, performing a second sorting operation on a plurality of second current sources according to current levels generated by the second current sources, determining a first switching sequence for the first plurality of current sources according to a result of the first sorting operation, and determining a second switching sequence for the second plurality of current sources according to a result of the second sorting operation and the first switching sequence. The plurality of first current sources have a same target current value, and the plurality of second current sources have a same target current value.

Abstract: A signal adjustment device includes a frequency adjustment circuit, a filter circuit, and a power estimation circuit. The frequency adjustment circuit is configured to receive a two-tone signal from a signal generator and to generate a first signal according to the two-tone signal, wherein the signal generator generates the two-tone signal according to a first coefficient and a second coefficient. The filter circuit is configured to filter the first signal, in order to generate a second signal. The power estimation circuit is configured to detect a power of an intermodulation distortion from the third order signal component, which is associated with the two-tone signal, in the second signal, and to adjust at least one of the first coefficient and the second coefficient according to the power, in order to reduce the power.

Abstract: The present application provides an image processing method and an image processing system. The image processing method includes: obtaining a first image matrix; generating a first classified image matrix, wherein the first classified image matrix Includes a plurality of parts corresponding to a plurality of classification; obtaining a plurality of weightings, for a first image process, corresponding to the plurality of parts of the first classified image matrix, and generating a first weighting matrix accordingly; and performing the first image process upon the first image matrix according to the first weighting matrix to generate a first processed image matrix.

Abstract: A time-interleaved analog to digital converter includes capacitor array circuits, at least one successive approximation register circuitry, and at least one noise shaping circuitry. The capacitor array circuits are configured to alternately sample an input signal, in order to generate a sampled input signal. The at least one successive approximation register circuitry is configured to perform an analog to digital conversion according to the sampled input signal and a residue signal, in order to generate at least one digital output. The at least one noise shaping circuitry is configured to utilize at least one first circuit in switched-capacitor circuits to transfer the residue signal from a first capacitor array circuit in the capacitor array circuits, and randomly select at least one second circuit from the switched-capacitor circuits to cooperate with a second capacitor array circuit in the capacitor array circuits to sample the input signal.

Abstract: The present disclosure discloses a multi-path image processing apparatus. An image merging circuit is configured to receive image frames that at least one of the image frames has a largest row number, generate redundant pixel row for each of the image frames that has a row number smaller than the largest row number such that the row number of each of the image frames equals to the largest row number, generate redundant pixel columns for each of the image frames having the number thereof determined by a size of a largest operation window, and merge each two of the image frames through the redundant columns thereof to generate a merged image frame. An image processing circuit performs image processing procedure on the merged image frame to generate a processed merged image frame, wherein at least a part of the image processing procedure is operated according to the largest operation window. An image segmentation circuit segments the processed merged image frame to generate processed image frames.

Abstract: A wireless access point includes a memory and a processor. The processor is configured to access instructions stored in the memory, and execute the instructions to perform following steps: periodically transmitting a plurality of beacons to a station so that the station operates in a low power sleep mode or an active mode based on the beacons, in which the beacons includes two successive beacons; and, between the transmission of the two successive beacons, determining whether to transmit a management frame to the station based on a traffic condition of packets being directed to the station so that the station establishes a mode switching in response to the management frame. The traffic condition includes a channel state and a number or a validity of the packets. The mode switching includes switching from one of the low power sleep mode and the active mode to another.

Abstract: An image processing method includes: downsizing a current frame and a reference frame; dividing the down-sized current frame and the down-sized reference frame into multiple first current blocks and multiple first reference blocks, respectively; performing a first motion estimation to the first current blocks and the first reference blocks to generate multiple first motion vectors; dividing the current picture and the reference picture into multiple second current blocks and multiple second reference blocks, respectively; performing a second motion estimation to the second current blocks and the second reference blocks to generate multiple second motion vectors; and generating a compensated frame between the current frame and the reference frame according to the second motion vectors. The second motion estimation includes: performing a 3D recursive search for each second current block; and adjusting multiple estimation parameters in the 3D recursive search according to the first motion vector.

Abstract: A method for a multidrop network system is provided. The method includes the following steps: transmitting, by a first node, a sleep request message to a second node; and determining, by the first node, whether to enter a sleep state from a wakeup state according to the condition in which the second node transmits a sleep acknowledge message in response to the sleep request message.

Abstract: An 8-shaped inductive coil device that includes a first and a second spiral coils and a connection segment structure is provided. The first spiral coil includes first metal segments and crossing connection segments disposed at a first and a second metal layers respectively and includes first connection terminals. The second spiral coil includes second connection terminals. The connection segment structure electrically couples the first and the second connection terminals. The first and the second spiral coils are disposed along an imaginary line passing through a central region of each of ranges surrounded by the first and the second spiral coils. The connection segment structure and the crossing connection segments electrically couple the part of the first metal segments substantially vertical to the imaginary line, and the connection segment structure and the crossing connection segments are disposed substantially on the imaginary line.