Abstract: A network interface device, an electronic device including same, and a method of operating same are provided. The network interface device is coupled to a host including a storage circuit. The network interface device includes a processing circuit and a packet receiving circuit which is used for receiving multiple network packets. The processing circuit performs the following steps: parsing the network packets to obtain multiple sequence numbers of the network packets; reordering the network packets based on the sequence numbers to generate reorder information; appending the reorder information to one of the network packets and generating packet order information, or generating the packet order information containing the reorder information; storing the packet order information in the storage circuit; and issuing an interrupt to the host. The packet receiving circuit or the processing circuit stores the network packets in the storage circuit before the processing circuit issues the interrupt.

Abstract: A storage circuit includes a first storage region, a second storage region, a third storage region, and a fourth storage region. The first storage region stores first firmware data. The second storage region stores second firmware data. The third storage region stores first state data corresponding to the first firmware data. The fourth storage region stores second state data corresponding to the second firmware data. One of the first firmware data and the second firmware data is executed based on the first state data and the second state data. In a situation that the first firmware data is executed, the second firmware data is updated if a firmware updating event occurs.

Abstract: A wireless communication system includes a transceiver circuit, a memory circuit, and a processor circuit. The transceiver circuit transmits data through subchannels that includes a first subchannel and a second subchannel. The memory circuit stores a lookup table that indicates corresponding relations between transmission rates and channel indicators.

Abstract: A multidrop network system includes N network devices including a master device and a plurality of slave devices. The N network devices synchronize their respective time zones in a synchronization phase, then jointly perform equalizer coefficient training in a training phase, and then obtain their respective transmission opportunities in turn in a data transmission phase. Each network device includes a channel equalizer trained in the training phase and used for processing data in the data transmission phase. In the training phase, the master device sends out a training notification to request the slave devices to enter the training phase; the master device performs the equalizer coefficient training after it transmits the training notification, and the slave devices perform the equalizer coefficient training after they receive the training notification. After the completion of the equalizer coefficient training, the master device sends out a beacon to start the data transmission phase.

Abstract: A voice capturing method includes following operations: storing, by a buffer, voice data from a plurality of microphones; determining, by a processor, whether a target speaker exists and whether a direction of the target speaker changes according to the voice data and target speaker information; inserting a voice segment corresponding to a previous tracking direction into a current position in the voice data to generate fusion voice data when the target speaker exists and the direction of the target speaker changes from the previous tracking direction to a current tracking direction; performing, by the processor, a voice enhancement process on the fusion voice data according to the current tracking direction to generate enhanced voice data; performing, by the processor, a voice shortening process on the enhanced voice data to generate voice output data; and playing, by a playing circuit, the voice output data.

Abstract: The present invention discloses a voltage conversion circuit having self-adaptive mechanism. A control branch includes a first resistor coupled between a second power supply and a control terminal, and a switch circuit that is coupled between the control terminal and a ground terminal and receives an input voltage from an input terminal to generate a control voltage at the control terminal. A voltage-withstanding P-type transistor circuit of an output branch is coupled between the second power supply and the output terminal that generates an output voltage and is controlled by the control voltage. A voltage-withstanding N-type transistor circuit of the output branch is coupled between the output terminal and the ground terminal and is controlled by an inverted input voltage. When the input voltage is at a first power domain high/low state, the output voltage is at a second power domain high/low state.

Abstract: A transmission-end impedance matching circuit operates according to a signal of an overvoltage signal source and includes a first level shifter, a voltage generating circuit, and an impedance matching circuit. The first level shifter generates a first conversion voltage according to a source signal and operates between a first high voltage and a ground voltage. The voltage generating circuit generates a second high voltage according to the first conversion voltage, the first high voltage, and a medium voltage. The impedance matching circuit includes a second level shifter, a transistor, and two resistors. The second level shifter generates a gate voltage according to the second high voltage, a low voltage, and an input signal. The transistor is turned on/off according to the gate voltage and has a withstand voltage lower than the first high voltage. Each of the two resistors is coupled between the transistor and a differential signal transmission end.

Abstract: A clock multiplexer device includes first and second control circuitries and an output circuitry. The first control circuitry generates a first enable signal and a first signal according to a first clock signal and a first selection signal, and determines whether to output the first signal to be a first output clock signal according to a second selection signal and a second enable signal. The first and the second selection signals have opposite logic values. The second control circuitry generates the second enable signal and a second signal according to a second clock signal and the second selection signal, and determines whether to output the second signal to be a second output clock signal according to the first selection signal and the first enable signal. The output circuitry outputs one of the first output clock signal and the second output clock signal to be a final clock signal.

Abstract: An audio playback method includes the following steps: receiving an ultrasound signal via a microphone; processing the ultrasound signal to obtain a characteristic value of the ultrasound signal; obtaining time lag information based on the characteristic value; and controlling audio delay according to the time lag information.

Abstract: An oscillation circuit including an amplifier, a feedback resistor and a first switch circuit is provided. The amplifier inverts and amplifies an oscillation signal received from an input terminal thereof to provide an output oscillation signal at an output terminal thereof. The feedback resistor is coupled between the input terminal and the output terminal, and coupled with the first switch circuit in parallel. The first switch circuit conducts the input terminal to the output terminal in one of the following situations: (1) an input voltage of the oscillation signal is higher than an output voltage of the output oscillation signal by at least a first threshold value; and (2) the output voltage is higher than the input voltage by at least a second threshold value. The first switch circuit has a first on-state resistance smaller than a resistance of the feedback resistor.

Abstract: An amplifier circuit includes a multistage amplifier, a first feedback circuit and a second feedback circuit. The multistage amplifier includes a first-staged amplifier, a last-staged amplifier and at least one middle-staged amplifier cascaded between the first-staged amplifier and the last-staged amplifier. The first feedback circuit is configured to couple a positive output end of the last-staged amplifier to a positive input end of the at least one middle-staged amplifier, or is configured to couple a negative output end of the last-staged amplifier to a negative input end of the at least one middle-staged amplifier. The second feedback circuit is configured to couple the positive output end of the last-staged amplifier to a positive input end of the last-staged amplifier, or is configured to couple the negative output end of the last-staged amplifier to a negative input end of the last-staged amplifier.

Abstract: A method for outputting a current includes performing a sorting operation on a plurality of current sources according to intensities of currents generated by the current sources, dividing the plurality of current sources into N current source sets according to a result of the sorting operation and a predetermined selection order, and enabling at least one current source set of the N current source sets to output the current according a target output value. The plurality of current sources have a same target current value. Each of the N current source sets includes at least one current source. In the N current source sets, a total quantity of current sources of the nth current source set is twice a total quantity of current sources of the (n?1)th current source set.

Abstract: An analog circuit including a voltage regulator, at least one analog-to-digital convertor (ADC), at least one comparator and a multiplexer is provided. The voltage regulator generates an output voltage. The at least one ADC generates at least one digital signal. The multiplexer is configured to conduct the at least one comparator to either the voltage regulator or the at least one ADC. When the voltage regulator is triggered, the multiplexer conducts the at least one comparator to the voltage regulator, and the voltage regulator generates the output voltage according to an output of the at least one comparator. When the at least one ADC is triggered, the multiplexer conducts the at least one comparator to the at least one ADC, and the at least one ADC generates the at least one digital signal according to the output of the at least one comparator.

Abstract: The present disclosure discloses a switched capacitor amplifier apparatus for improving level-shifting. An amplifier includes input terminals and output terminals. Two capacitor circuits correspond to signal input terminals and signal output terminals and each includes a sampling capacitor circuit, a load capacitor and a level-shifting capacitor. The sampling capacitor circuit samples an input signal from one of the signal input terminals to one of the input terminals. An electrical charge neutralizing capacitor is coupled between the output terminals. The load capacitor and the level-shifting capacitor are charged according to an output from one of the output terminals in an estimation period. The level-shifting capacitor charges the load capacitor in a level-shifting period to generate an output signal at one of the signal output terminals.

Abstract: A pipeline analog to digital converter includes converter circuitries and a calibration circuitry. The converter circuitries sequentially convert an input signal into first digital codes. A first converter circuitry in the converter circuitries performs a quantization according to a first signal to generate a first corresponding digital code in the first digital codes, and the first signal is a signal, which is processed by the first converter circuitry, of the input signal and a previous stage residue signal. The calibration circuitry combines the first digital codes to output a second digital code, detects whether the quantization is completed to generate first and second valid signals, and determines whether to set the second digital code to be a first predetermined digital code or a second predetermined digital code according to the first and the second valid signals. The second valid signal is a delay signal of the first valid signal.

Abstract: A file reading method includes following operations: determining, by a processor, whether a file in a SIM card is stored in a non-volatile memory; performing, by the processor, a reading process to read the file from the SIM card if the file is not stored in the non-volatile memory; and storing, by the processor, the file into the non-volatile memory.

Abstract: A data transmission method includes: starting transferring chunks in a first data block of an image file to a device via a Bluetooth network; when a number of at least one first trunk in the chunks that has been transferred to the device equals to a transfer window, determining whether the device receives all of the at least one first trunk to update the chunk missing data; if the device receives all of the at least one first trunk, dynamically adjusting the transfer window according to the chunk missing data to continue transferring remaining chunks in the chunks or a second data block of the image file to the device; and if the device fails to receive all of the at least one first trunk, retransferring at least one chunk that is not previously received by the first device to the device.

Abstract: The present invention discloses a Bluetooth mesh network system having a communication range extending mechanism that includes a plurality of nodes and a provisional node. The provisional node is configured to transmit a connection setting packet to the nodes to control the nodes to establish a coded PHY connection between each two of the nodes such that a packet error rate is smaller than a threshold value when the nodes perform communication when a physical distance between each two of the nodes is larger than a maximum non-coded-PHY communication distance, in which when the nodes establish a non-coded-PHY connection and the physical distance is larger than the maximum non-coded-PHY communication distance, the packet error rate is larger than the threshold value.

Abstract: A signal processing circuit includes an input buffer circuit and a direct-(DC) voltage detector circuit. The input buffer circuit is coupled to a pin. The pin is configured to receive an input signal. The DC voltage detector circuit is coupled to the pin and the input buffer circuit. The DC voltage detector circuit is configured to detect the input signal to generate a mode signal and generate a bias of the input buffer circuit according to the mode signal.

Abstract: A phase interpolator includes phase interpolator circuitries. The phase interpolator circuitries generate an output clock signal from an output node according to phase control bits and clock signals. Phases of the clock signals are different from each other. Each phase circuitry includes phase buffer circuits. Each phase buffer circuit is turned on according a first bit and a second bit of the phase control bits, in order to generate a signal component in the output clock signal according to a corresponding clock signal of the clock signals. Each phase buffer circuit includes a first resistor and a second resistor, and transmits one of a first voltage and a second voltage to the output node according to the corresponding clock signal, in which the first voltage is transmitted to the output node via the first resistor, and the second voltage is transmitted to the output node via the second resistor.